TM4C129LNCZAD Datasheet, PDF (1080/2140 Pages) Texas Instruments – Tiva Microcontroller

SHA/MD5 Accelerator
Register 1: SHA Outer Digest A (SHA_ODIGEST_A), offset 0x000
Register 2: SHA Outer Digest B (SHA_ODIGEST_B), offset 0x004
Register 3: SHA Outer Digest C (SHA_ODIGEST_C), offset 0x008
Register 4: SHA Outer Digest D (SHA_ODIGEST_D), offset 0x00C
Register 5: SHA Outer Digest E (SHA_ODIGEST_E), offset 0x010
Register 6: SHA Outer Digest F (SHA_ODIGEST_F), offset 0x014
Register 7: SHA Outer Digest G (SHA_ODIGEST_G), offset 0x018
Register 8: SHA Outer Digest H (SHA_ODIGEST_H), offset 0x01C
Register 9: SHA Inner Digest A (SHA_IDIGEST_A), offset 0x020
Register 10: SHA Inner Digest B (SHA_IDIGEST_B), offset 0x024
Register 11: SHA Inner Digest C (SHA_IDIGEST_C), offset 0x028
Register 12: SHA Inner Digest D (SHA_IDIGEST_D), offset 0x02C
Register 13: SHA Inner Digest E (SHA_IDIGEST_E), offset 0x030
Register 14: SHA Inner Digest F (SHA_IDIGEST_F), offset 0x034
Register 15: SHA Inner Digest G (SHA_IDIGEST_G), offset 0x038
Register 16: SHA Inner Digest H (SHA_IDIGEST_H), offset 0x03C
PKA Status Register
SHA Outer Digest n (SHA_ODIGEST_n)
Base 0x4403.4000
Offset 0x000
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DATA
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:0
Name
DATA
Type
Reset Description
RW 0x0000.0000 Digest/Key Data
1080
Texas Instruments-Production Data
June 18, 2014