SMJ44C256 Datasheet, PDF (9/21 Pages) Texas Instruments – 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY

SMJ44C256
262144 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating temperature
(continued) (see Note 5)
PARAMETER
td(CARH)
Delay time, column address to
RAS high
ALT.
SYMBOL
tRAL
’44C256-80 ’44C256-10 ’44C256-12 ’44C256-15
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
40
45
55
70
ns
Delay time, column address to
td(CACH) _{CAS high}
tCAL
40
45
55
70
ns
td(RLWL)
Delay time, RAS low to W low
(see Note 14)
tRWD
130
150
170
200
ns
td(CAWL)
Delay time, column address to W
low (see Note 14)
tAWD
80
td(GHD)
Delay time, G high before data at
DQ
tGDD
20
95
105
120
ns
25
30
40
ns
td(GLRH) Delay time, G low to RAS high
tGSR
20
25
30
40
ns
td(RLCH)R
Delay time, RAS low to CAS high
(see Note 16)
tCHR
20
25
25
30
ns
td(CLRL)R
Delay time, CAS low to RAS low
(see Note 16)
tCSR
10
10
10
td(RHCL)R
Delay time, RAS high to CAS low
(see Note 16)
tRPC
0
0
0
trf
Refresh time interval
tREF
8
8
tt
Transition time (see Note 17)
tT
NOTES: 5. Timing measurements in this table are referenced to VIL max and VIH min.
14. Read-modify-write operation only
16. CBR refresh only
17. System transition times (rise and fall) are to be a minimum of 3 ns and a maximum of 50 ns.
15
0
8
ns
ns
8 ms
ns
Output Under Test
PARAMETER MEASUREMENT INFORMATION
1.31 V
RL = 218 Ω
CL = 80 pF
(See Note A)
Output Under Test
CL = 80 pF
(See Note A)
5V
R1 = 828 Ω
R2 = 295 Ω
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
NOTE A: CL includes probe and fixture capacitance.
Figure 1. Load Circuits for Timing Parameters
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