SMJ44C256 Datasheet, PDF (15/21 Pages) Texas Instruments – 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY

SMJ44C256
262144 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
RAS
tw(RL)P
tw(RH)
CAS
A0 – A8
W
DQ1–DQ4
td(RLCH)
td(RLCL)
tw(CL)
tc(P)
tw(CH)
td(CLRH)
td(CHRL)
tsu(RA)
tsu(CA)
th(RA)
th(RLCA)
th(CA)
Row
Column
td(CACH)
td(CARH)
Column
Don’t Care
td(RLCA)
th(RLW)
tw(WL)
Don’t Care
tsu(WCH)
tsu(WCH)
Don’t Care
tsu(WRH)
Don’t Care
tsu(D)
(see Note B)
tsu(D)
(see Note B)
th(RLD)
th(D)
(see Note B)
th(D)
(see Note B)
Valid Data In
Valid In
th(WLGL)
Don’t Care
td(GHD)
G
th(WLGL)
Don’t Care
td(GHD)
Don’t Care
NOTES: A. A read cycle or a read-modify-write cycle can be intermixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated.
B. Referenced to CAS or W, whichever occurs last.
Figure 7. Enhanced-Page-Mode Write-Cycle Timing (see Note A)
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