SMJ44C256 Datasheet, PDF (4/21 Pages) Texas Instruments – 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY

SMJ44C256
262144 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
address (A0 through A8)
Eighteen address bits are required to decode 1 of 262 144 storage cell locations. Nine row-address bits are set
up on pins A0 through A8 and latched onto the chip by RAS. Nine column-address bits are set up on pins A0
through A8 and latched onto the chip by CAS. All addresses must be stable on or before the falling edges of
RAS and CAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder.
In the SMJ44C256, CAS is used as a chip select, activating the output buffer as well as latching the address
bits into the column-address buffers.
write enable (W)
The read or write mode is selected through W. A logic high on the W input selects the read mode and a logic
low selects the write mode. The write-enable terminal can be driven from the standard TTL circuits without a
pullup resistor. The data input is disabled when the read mode is selected. When W goes low prior to CAS
(early-write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
G grounded.
data in (DQ1–DQ4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS and
the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or
read-modify-write cycle, CAS is already low, the data is strobed in by W with setup and hold times referenced
to this signal. In a delayed-write or read-modify-write cycle, G must be high to bring the output buffers to the
high-impedance state prior to applying data to the I/O lines.
data out (DQ1–DQ4)
The 3-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS and G are brought low. In a read cycle the output becomes valid after the access time interval t_a(C)
that begins with the negative transition of CAS as long as t_a(R) and t_a(CA) are satisfied. The output becomes valid
after the access time has elapsed and remains valid while CAS and G are low. CAS or G going high returns it
to a high-impedance state. This is accomplished by bringing G high prior to applying data, thus satisfying t_d(GHD).
output enable (G)
G controls the impedance of the output buffers. When G is high, the buffers remain in the high-impedance state.
Bringing G low during a normal cycle activates the output buffers, putting them in the low-impedance state. It
is necessary for both G and CAS to be brought low for the output buffers, to go into the low-impedance state.
Once in the low-impedance state, they remain in the low-impedance state until either G or CAS is brought high.
refresh
A refresh operation must be performed at least once every 8 ms to retain data. This can be achieved by strobing
each of the 512 rows (A0 – A8). A normal read or write cycle refreshes all bits in each row that is selected. A
RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh. Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished
by holding CAS at V_IL after a read operation and cycling RAS after a specified precharge period, similar to a
RAS-only refresh cycle.
CBR refresh
CBR refresh is utilized by bringing CAS low earlier than RAS [see parameter t_d(CLRL)R] and holding it low after
RAS falls [see parameter t_d(RLCH)R]. For successive CBR refresh cycles, CAS can remain low while cycling
RAS. The external address is ignored and the refresh address is generated internally. The external address is
also ignored during the hidden refresh option.
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