SMJ44C256 Datasheet, PDF (7/21 Pages) Texas Instruments – 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY

SMJ44C256
262144 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
PARAMETER
ALT.
SYMBOL
’44C256-80
MIN MAX
’44C256-10
MIN MAX
’44C256-12
MIN MAX
’44C256-15
MIN MAX
UNIT
ta(C)
ta(CA)
ta(RL)
ta(G)
ta(CP)
Access time from CAS low
Access time from column-address
Access time from RAS low
Access time from G low
Access time from CAS high column
precharge
tCAC
tAA
tRAC
tGAC
tCPA
20
25
30
40 ns
40
45
55
70 ns
80
100
120
150 ns
20
25
30
40 ns
40
50
60
75 ns
tdis(CH)
Output disable time after CAS high
(see Note 4)
tOFF
20
25
30
35 ns
tdis(G)
Output disable time after G high
(see Note 4)
tGOFF
20
25
30
35 ns
NOTE 4: tdis(CH) and tdis(G) are specified when the output is no longer driven. The outputs are disabled by bringing either G or CAS high.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
PARAMETER
ALT.
SYMBOL
’44C256-80
MIN MAX
’44C256-10
MIN MAX
’44C256-12
MIN MAX
’44C256-15
UNIT
MIN MAX
tc(rd)
Cycle time, read (see Note 6)
tRC
150
190
220
260
ns
tc(W)
Cycle time, write
tWC
150
190
220
260
ns
Cycle time,read-write / read-
tc(rdW) _modify-write
tRWC
225
270
305
355
ns
tc(P)
Cycle time, page-mode read
or write (see Note 7)
tPC
50
55
65
80
ns
tc(PM)
Cycle time, page-mode read-
modify-write
tPRWC
115
135
150
175
ns
tw(CH)
tw(CL)
Pulse duration, CAS high
Pulse duration, CAS low
(see Note 8)
tCP
tCAS
10
20 10 000
10
25 10 000
15
30 10 000
25
ns
40 10 000 ns
Pulse duration, RAS high
tw(RH)
(precharge)
tRP
60
80
90
100
ns
tw(RL)
Pulse duration,
nonpage mode RAS low
(see Note 9)
tRAS
80 10 000 100 10 000 120 10 000 150 10 000 ns
tw(RL)P
Pulse duration,
page mode RAS low
(see Note 9)
tRASP
80 100 000 100 100 000 120 100 000 150 100 000 ns
tw(WL) Pulse duration, write low
tWP
15
15
20
25
ns
Setup time, column address
tsu(CA) _{before CAS low}
tASC
5
5
5
5
ns
NOTES:
5. Timing measurements in this table are referenced to VIL max and VIH min.
6. All cycle times assume tt = 5 ns.
7. To assure tc(P) min, tsu(CA) should be ≥ tw(CH).
8. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user’s transition times, this can require
additional CAS low time [tw(CL)].
9. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user’s transition times, this can require
additional RAS low time [tw(RL)].
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