SMJ44C256 Datasheet, PDF (8/21 Pages) Texas Instruments – 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY

SMJ44C256
262144 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating temperature
(continued) (see Note 5)
PARAMETER
ALT.
’44C256-80 ’44C256-10 ’44C256-12
SYMBOL _{MIN MAX MIN MAX MIN MAX}
tsu(RA)
Setup time, row address
before RAS low
tASR
0
0
0
tsu(D)
Setup time, data before
W low (see Note 10)
tDS
0
0
0
tsu(rd)
Setup time, W high before CAS low
tRCS
0
0
0
tsu(WCL)
Setup time, W low before CAS low
(see Note 11)
tWCS
0
0
0
tsu(WCH) Setup time, W low before CAS high
tCWL
20
25
30
tsu(WRH) Setup time, W low before RAS high
tRWL
20
25
30
th(CA)
Hold time, column address after CAS
low (see Note 10)
tCAH
15
20
20
th(RA)
Hold time, row address after RAS
low
tRAH
15
15
15
th(RLCA)
Hold time, column address after RAS
low (see Note 12)
tAR
60
70
80
th(D)
Hold time, data after CAS low
(see Note 10)
tDH
15
20
25
th(RLD)
Hold time, data after RAS low
(see Note 12)
tDHR
60
70
85
th(WLGL) Hold time, G high after W low
tGH
20
25
30
th(CHrd)
Hold time, W high after CAS high
(see Note 13)
tRCH
0
0
0
th(RHrd)
Hold time, W high after RAS high
(see Note 13)
tRRH
10
10
10
th(CLW)
Hold time, W low after CAS low
(see Note 11)
tWCH
15
20
25
th(RLW)
Hold time, W low after RAS low
(see Note 12)
tWCR
65
75
90
td(RLCH) Delay time, RAS low to CAS high
tCSH
80
100
120
td(CHRL) Delay time, CAS high to RAS low
tCRP
0
0
0
td(CLRH) Delay time, CAS low to RAS high
tRSH
20
25
30
td(CLWL)
Delay time, CAS low to W low
(see Note 14)
tCWD
60
70
80
td(RLCL)
Delay time, RAS low to CAS low
(see Note 15)
tRCD
30
60
30
75
30
90
td(RLCA)
Delay time, RAS low to column
address (see Note 15)
tRAD
20
40
20
55
20
65
NOTES: 5. Timing measurements in this table are referenced to VIL max and VIH min.
10. Referenced to the later of CAS or W in write operations.
11. Early-write operation only
12. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
13. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.
14. Read-modify-write operation only
15. Maximum value specified only to assure access time.
’44C256-15
MIN MAX
0
0
0
0
40
40
25
15
100
30
110
40
0
10
30
105
150
0
40
90
30 110
25
80
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
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