SMJ44C256 Datasheet, PDF (14/21 Pages) Texas Instruments – 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY

SMJ44C256
262144 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
RAS
tw(RL)P
tw(RH)
CAS
A0 – A8
W
DQ1–DQ4
G
td(RLCL)
td(RLCH)
tw(CL)
tc(P)
tw(CH)
td(CLRH)
td(CHRL)
tsu(RA)
th(RA)
th(RLCA)
tsu(CA)
th(CA)
td(CACH)
td(CARH)
Row
td(RLCA)
tsu(rd)
Don’t Care
Column
Don’t Care
Column
Don’t Care
th(RHrd)
th(CHrd)
ta(C)
ta(R)
ta(CA)
See Note A
Valid Out
ta(CA)
(see Note A)
ta(CP)
(see Note C)
See Note A
Valid Out
tdis(CH)
ta(G)
tdis(G)
Don’t Care
ta(G)
tdis(G)
Don’t Care
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A write-cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
C. Access time is ta(CP)- or ta(CA)-dependent.
Figure 6. Enhanced-Page-Mode Read-Cycle Timing
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