SMJ44C256 Datasheet, PDF (16/21 Pages) Texas Instruments – 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY

SMJ44C256
262144 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
RAS
tw(RL)P
tw(RH)
CAS
td(RLCL)
tsu(RA)
td(RLCH)
tc(PM)
tw(CL)
tsu(CA)
td(RLCA)
th(RLCA)
th(CA)
td(CLRH)
tw(CH)
td(CHRL)
A0 – A8
Row
Column
Column
Don’t Care
th(RA)
W
DQ1–DQ4
tsu(rd)
ta(CA)
ta(R)
Don’t Care
td(CLWL)
td(CAWL)
td(RLWL)
ta(C)
See Note A
Valid Out
tsu(WCH)
tw(WL)
tsu(WRH)
ta(CP)
tsu(D)
th(D)
See Note A
Valid In
Valid
Out
th(WLGL)
Don’t Care
ta(G)
td(GHD)
tdis(G)
G
th(WLGL)
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not
violated.
Figure 8. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing (see Note B)
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