SMJ44C251 Datasheet, PDF (9/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
RAS-only refresh
A refresh operation must be performed to each row at least once every 8 ms to retain data. Unless CAS is
applied, the output buffers are in the high-impedance state, so the RAS-only refresh sequence avoids any
output during refresh. Externally generated addresses must be supplied during RAS-only refresh. Strobing each
of the 512 row addresses with RAS causes all bits in each row to be refreshed. CAS can remain high (inactive)
for this refresh sequence to conserve power.
CAS-before-RAS (CBR) refresh
CBR refresh is accomplished by bringing CAS low earlier than RAS. The external row address is ignored and
the refresh row address is generated internally when using CBR refresh. Other cycles can be performed in
between CBR cycles without disturbing the internal address generation.
hidden refresh
A hidden refresh is accomplished by holding CAS low in the DRAM-read cycle and cycling RAS. The output data
of the DRAM-read cycle remains valid while the refresh is being carried out. Like the CBR refresh, the refreshed
row addresses are generated internally during the hidden refresh.
write-per-bit
The write-per-bit feature allows masking of any combination of the four DQs on any write cycle (see Figure 1).
The write-per-bit operation is invoked only when W is held low on the falling edge of RAS. If W is held high on
the falling edge of RAS, write-per-bit is not enabled and the write operation is performed to all four DQs. The
SMJ44C251B offers two write-per-bit modes: the nonpersistent write-per-bit mode and the persistent
write-per-bit mode.
nonpersistent write-per-bit
When DSF is low on the falling edge of RAS, the write mask is reloaded. A 4-bit code (the write-per-bit mask)
is input to the device via the random DQ terminals and latched on the falling edge of RAS. The write-per-bit mask
selects which of the four random I/Os are written and which are not. After RAS has latched the on-chip
write-per-bit mask, input data is driven onto the DQ terminals and is latched on the later falling edge of CAS or
W. When a data low is strobed into a particular I/O on the falling edge of RAS, data is not written to that I/O. When
a data high is strobed into a particular I/O on the falling edge of RAS, data is written to that I/O.
persistent write-per-bit
When DSF is high on the falling edge of RAS, the write-per-bit mask is not reloaded: it retains the value stored
during the last write-per-bit mask reload. This mode of operation is known as persistent write-per-bit because
the write-per-bit mask is persistent over an arbitrary number of write cycles. The write-per-bit mask reload can
be done during the nonpersistent write-per-bit cycle or by the mask-register-load cycle.
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
9