SMJ44C251 Datasheet, PDF (8/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
random-access operation
The random-access operation functions are summarized in Table 2 and described in the following sections.
Table 2. Random-Access-Operation Functions
FUNCTION
CBR refresh
Load and use write mask,
Write data to DRAM
Load and use write mask,
Block write to DRAM
Persistent write-per-bit,
Write data to DRAM
Persistent write-per-bit,
Block write to DRAM
Normal DRAM read / write
(nonmasked)
Block write to DRAM
(nonmasked)
Load write mask
RAS FALL
CAS
FALL
CAS TRG W† DSF SE DSF
L
X
X
X
X
X
H
H
L
L
X
L
H
H
L
L
X
H
H
H
L
H
X
L
H
H
L
H
X
H
H
H
H
L
X
L
H
H
H
L
X
H
H
H
H
H
X
L
Load color register
H
H
H
H
X
H
Legend:
H = High
L = Low
X = Don’t care
† _{In persistent write-per-bit function, W must be high during the refresh cycle.}
‡ _{DQ0 – DQ3 are latched on the later of W or CAS falling edge.}
Col Mask = H: Write to address/column location enabled
DQ Mask = H: Write to I/O enabled
ADDRESS
RAS
X
Row
Addr
Row
Addr
Row
Addr
Row
Addr
Row
Addr
Row
Addr
Refresh
Addr
Refresh
Addr
CAS
X
Col
Addr
Blk Addr
A2 – A8
Col
Addr
Blk Addr
A2 – A8
Col
Addr
Blk Addr
A2 – A8
X
X
DQ0 – DQ3
RAS
X
DQ
Mask
DQ
Mask
X
X
X
X
X
X
CAS‡
W
X
Valid
Data
Col
Mask
Valid
Data
Col
Mask
Valid
Data
Col
Mask
DQ
Mask
Color
Data
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. This mode eliminates the time required for row address setup-and-hold and
address multiplex. The maximum RAS low time and the CAS page cycle time used determine the number of
columns that can be accessed.
Unlike conventional page-mode operation, the enhanced page mode allows the SMJ44C251B to operate at a
higher data bandwidth. Data retrieval begins as soon as the column address is valid rather than when CAS
transitions low. A valid column address can be presented immediately after row-address hold time has been
satisfied, usually well in advance of the falling edge of CAS. In this case, data can be obtained after t_a(C) max
(access time from CAS low), if t_a(CA) max (access time from column address) has been satisfied.
refresh
There are three types of refresh available on the SMJ44C251B: RAS-only refresh, CBR refresh, and hidden
refresh.
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