SMJ44C251 Datasheet, PDF (45/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

RAS
CAS
A0 – A8
DSF
TRG
W
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tw(RL)
td(RLCL)
tc( _TRD)
td(CHRL)
td(RLCH)
td(CARH)
td(RLCA)
tw(CL)
tsu(RA)
th(SFR)
th(RLCA)
th(RA)
th(CLCA)
tsu(CA)
Row
Tap Point
A0 – A8
td(CAGH)
tw(RH)
Don’t Care
tsu(SFR)
tsu( _{TRG) td(CLGH)}
th( _TRG)
tsu( _WMR)
th(RWM)
td(RLTH)
Don’t Care
td( _THRH)
td( _THRL)
tw(GH)
Don’t Care
Don’t Care
DQ0 – DQ3
td(SCRL)
Hi-Z
td(CLSH)
td(RLSH)
td( _THSC)
SC
tsu(SDS)
SDQ0 – SDQ3
Valid In
td(SDRL)
th(SDS)
Invalid Out
tc(SC)
ta(SQ)
Valid Out
td(GHQSF)
QSF
Tap Point bit A7
H
SE
L
td(CLQSF)
td(RLQSF)
NOTES: A. Late-load operation is defined as td( _THRH) < 0 ns.
B. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register
transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register are written
from the 512 corresponding columns of the selected row. The data that is transferred into the data registers may be either shifted
out or transferred back into another row.
C. Once data is transferred into the data registers, the SAM is in the serial read mode (i.e., SQ is enabled), allowing data to be shifted
out of the registers. Also, the first bit to be read from the data register after TRG has gone high must be activated by a positive
transition of SC.
Figure 33. Memory-to-Data-Register Transfer-Cycle Timing, SDQ Ports Previously in Serial-Input Mode
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