SMJ44C251 Datasheet, PDF (7/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
serial enable (SE)
During serial-access operations SE is used as an enable/disable for SDQ in both the input and output modes.
If SE is held as RAS falls during a write-transfer cycle, a pseudo-transfer write occurs. There is no actual transfer,
but the data register switches from the output mode to the input mode.
no connect / ground (NC/GND)
NC/GND is reserved for the manufacturer’s test operation. It is an input and should be tied to system ground
or left floating for proper device operation.
special function output (QSF)
During split-register operation the QSF output indicates which half of the SAM is being accessed. When QSF
is low, the serial-address pointer is accessing the lower (least significant) 256 bits of SAM. When QSF is high,
the serial-address pointer is accessing the higher (most significant) 256 bits of SAM. QSF changes state upon
crossing the boundary between the two SAM halves in the split-register mode.
During normal transfer operations QSF changes state upon completing a transfer cycle. This state is determined
by the tap point being loaded during the transfer cycle.
power up
To achieve proper device operation, an initial pause of 200 µs is required after power-up, followed by a minimum
of eight RAS cycles or eight CBR cycles, a memory-to-register transfer cycle, and two SC cycles.
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