SMJ44C251 Datasheet, PDF (5/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
operation
Depending on the type of operation chosen, the signals of the SMJ44C251B perform different functions.
Table 1 summarizes the signal descriptions and the operational modes they control.
Table 1. Detailed Signal Description Versus Operational Mode
PIN
DRAM
TRANSFER
SAM
A0 – A8 Row, column address
Row, tap address
CAS
Column enable, output enable
Tap-address strobe
DQi
DRAM data I/O, write mask bits
DSF
Block-write enable
Persistent write-per-bit enable
Color-register load enable
Split-register enable
Alternate write-transfer enable
RAS
Row enable
Row enable
SE
Serial-in mode enable
Serial enable
SC
Serial clock
SDQ
Serial-data I/O
TRG
Q output enable
Transfer enable
W
Write enable, write-per-bit select
Transfer-write enable
QSF
Split register
Active status
NC/GND
VCC
VSS
Make no external connection or tie to system VSS.
5-V supply (typical)
Device ground
The SMJ44C251B has three kinds of operations: random-access operations typical of a DRAM, transfer
operations from memory arrays to the SAM, and serial-access operations through the SAM port. The signals
used to control these operations are described here, followed by discussions of the operations themselves.
address (A0 – A8)
For DRAM operation, 18 address bits are required to decode one of the 262 144 storage cell locations. Nine
row-address bits are set up on A0 – A8 and latched onto the chip on the falling edge of RAS. Nine
column-address bits are set up on A0 – A8 and latched onto the chip on the falling edge of CAS. All addresses
must be stable on or before the falling edges of RAS and CAS.
During the transfer operation, the states of A0 – A8 are latched on the falling edge of RAS to select one of the
512 rows where the transfer occurs. To select one of 512 tap points (starting positions) for the serial-data input
or output, the appropriate 9-bit column address (A0 – A8) must be valid when CAS falls.
row-address strobe (RAS)
RAS is similar to a chip enable because all DRAM cycles and transfer cycles are initiated by the falling edge
of RAS. RAS is a control input that latches the states of row address, W, TRG, SE, CAS, and DSF onto the chip
to invoke DRAM and transfer functions.
column-address strobe (CAS)
CAS is a control input that latches the states of column address and DSF to control DRAM and transfer functions.
When CAS is brought low during a transfer cycle, it latches the new tap point for the serial-data input or output.
CAS also acts as an output enable for the DRAM outputs DQ0 – DQ3.
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
5