SMJ44C251 Datasheet, PDF (31/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
RAS
td(CHRL)
CAS
tsu(RA)
th(RA)
tw(RL)P
td(RLCL)
td(RLCH)
tc(rdWP)
tw(CL)
td(RLCA)
tsu(CA)
th(RLCA)
th(CLCA)
td(CLRH)
tw(CH)
td(CHRL)
td(CARH)
tw(RH)
A0 – A8
Row
Column
Column
tsu(SFR)
DSF
1
th(SFR)
tsu(SFC)
2
th(SFC)
tsu(SFC)
2
th(SFC)
th( _TRG)
tsu( _TRG)
tsu(rd)
td(CLWL)
td(CAWL)
td(RLWL)
td(CLGH)
tw( _TPG)
tsu( _WRH)
td(DCL)
td(CLGH)
tsu( _WCH)
TRG
th(RWM)
tsu( _WMR)
ta(C)†
tw( _WL)
tw( _TRG)
td(GHD)
W
3
ta(CA)†
tsu(DQR)
th(RDQ)
td(DCL)
tsu(DWL)
th( _WLD)
ta(CP)†
tsu(DWL)
th( _WLD)
DQ0 – DQ3
4
Valid
Out
5
Valid
Out
5
td(DGL)
ta(R)
ta(G)†
td(DGL)
td(GHD)
ta(C)†
tdis(G)
† _{Output can go from the high-impedance state to an invalid data state prior to the specified access time.}
NOTE A: A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not violated.
Figure 19. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing
Table 8. Write-Cycle State Table
CYCLE
Write operation
Write-mask load/use, write DQs to I/Os
Use previous write mask, write DQs to I/Os
Load write mask on later of W fall and CAS fall
1
2
L
L
L
L
H
L
H
L
STATE
3
H
L
L
H
4
Don’t care
Write mask
Don’t care
Don’t care
5
Valid data
Valid data
Valid data
Write mask
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