SMJ44C251 Datasheet, PDF (30/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
RAS
CAS
tsu(RA)
td(RLCH)
td(RLCL)
td(CHRL)
tw(CL)
tsu(CA)
th(RA)
td(RLCA)
th(RLCA)
tw(RL)P
tc(P)
tw(CH)
tw(RH)
td(CLRH)
td(CHRL)
th(CLCA)
td(CARH)
A0 – A8
tsu(SFR)
DSF
Row
tsu(SFC)
th(SFR)
1
Column
th(RSF)
th(SFC)
2
Column
tsu(SFC)
th(SFC)
2
TRG
W
tsu(DQR)
tsu( _TRG)
th( _TRG)
tsu( _WCH)
tsu( _WMR)
tsu(RWM)
3
tw( _WL)
See Note A
tsu( _WCH)
tsu(DWL)†
tsu(DCL)†
th(RDQ)
th(RLD)
th(CLD)†
th( _WLD)†
tsu( _WRH)
DQ0 – DQ3
4
5
5
† _{Referenced to CAS or W, whichever occurs last}
NOTE B: A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing
specifications. TRG must remain high throughout the entire page-mode operation to assure page-mode cycle time if the late-write
feature is used. If the early-write-cycle timing is used, the state of TRG is a don’t care after the minimum period th( _TRG) from the falling
edge of RAS.
Figure 18. Enhanced-Page-Mode Write-Cycle Timing
Table 7. Write-Cycle State Table
CYCLE
Write operation
Write-mask load/use, write DQs to I/Os
Use previous write mask, write DQs to I/Os
Load write mask on later of W fall and CAS fall
1
2
L
L
L
L
H
L
H
L
STATE
3
H
L
L
H
4
Don’t care
Write mask
Don’t care
Don’t care
5
Valid data
Valid data
Valid data
Write mask
30
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443