SMJ44C251 Datasheet, PDF (2/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
pinouts
HJ PACKAGE
( TOP VIEW )
HM PACKAGE
( TOP VIEW )
SC 1 28 ^VSS
SDQ0 2 27 SDQ3
SDQ1 3 26 SDQ2
TRG 4 25 ^SE
DQ0 5 24 DQ3
DQ1 6 23 DQ2
W 7 22 DSF
GND 8 21 ^CAS
RAS 9 20 QSF
A8 10 19 A0
A6 11 18 A1
A5 12 17 A2
A4 13 16 A3
V_{CC 14 15 A7}
SC
SDQ0
SDQ1
TRG
DQ0
DQ1
W
GND
RAS
A8
A6
A5
A4
V_CC
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
V_SS
SDQ3
SDQ2
SE
DQ3
DQ2
DSF
CAS
QSF
A0
A1
A2
A3
A7
JD PACKAGE
( TOP VIEW )
SC 1 28 ^VSS
SDQ0 2 27 SDQ3
SDQ1 3 26 SDQ2
TRG 4 25 ^SE
DQ0 5 24 DQ3
DQ1 6 23 DQ2
W 7 22 DSF
GND 8 21 ^CAS
RAS 9 20 QSF
A8 10 19 A0
A6 11 18 A1
A5 12 17 A2
A4 13 16 A3
V_{CC 14 15 A7}
SV PACKAGE
( TOP VIEW )
DSF ¹
DQ3 ³
SDQ2 ⁵
2 DQ2
4 SE
VSS
SDQ0
TRG
DQ1
GND
A8
7
9
11
13
15
17
6 SDQ3
8 SC
10 SDQ1
12 DQ0
14 W
16 RAS
A5 ^{19 18 A8}
V_CC
A3
A1
QSF
21
23
25
27
20 A4
22 A7
24 A2
26 A0
28 CAS
description (continued)
During a transfer operation, the 512 columns of the DRAM are connected to the 512 positions in the serial data
register. The 512 × 4-bit serial-data register can be loaded from the memory row (transfer read), or the contents
of the 512 × 4-bit serial-data register can be written to the memory row (transfer write).
The SMJ44C251B is equipped with several features designed to provide higher system-level bandwidth and
to simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel draw rates
can be achieved by the device’s 4 × 4 block-write mode. The block-write mode allows four bits of data (present
in an on-chip color-data register) to be written to any combination of four adjacent column-address locations.
As many as 16 bits of data can be written to memory during each CAS cycle time. Also on the DRAM port, a
write mask or a write-per-bit feature allows masking any combination of the four input /outputs on any write cycle.
The persistent write-per-bit feature uses a mask register that, once loaded, can be used on subsequent write
cycles. The mask register eliminates having to provide mask data on every mask-write cycle.
The SMJ44C251B offers a split-register transfer read (DRAM to SAM) feature for the serial tester (SAM port).
This feature enables real-time register reload implementation for truly continuous serial data streams without
critical timing requirements. The register is divided into a high half and a low half. While one half is being read
out of the SAM port, the other half can be loaded from the memory array. For applications not requiring real-time
register reload (for example, reloads done during CRT retrace periods), the single-register mode of operation
is retained to simplify design. The SAM can also be configured in input mode, accepting serial data from an
external device. Once the serial register within the SAM is loaded, its contents can be transferred to the
corresponding column positions in any row in memory in a single memory cycle.
The SAM port is designed for maximum performance. Data can be input to or accessed from the SAM at serial
rates up to 33 MHz. During the split-register mode of operation, internal circuitry detects when the last bit
position is accessed from the active half of the register and immediately transfers control to the opposite half.
A separate output, QSF, is included to indicate which half of the serial register is active at any given time in the
split-register mode.
All inputs, outputs, and clock signals on the SMJ44C251B are compatible with Series 54 TTL devices. All
address lines and data-in lines are latched on-chip to simplify system design. All data-out lines are unlatched
to allow greater system flexibility.
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