SMJ44C251 Datasheet, PDF (22/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)^†
ALT.
’44C251B - 10
SYMBOL _MIN
MAX
tsu( _WCH) Setup time, write before CAS high
tCWL
25
tsu( _WRH) Setup time, write before RAS high with TRG = W = low
tRWL
25
tsu(SDS) Setup time, SDQ before SC high
tSDS
0
th(CLCA) Hold time, column address after CAS low
tCAH
20
th(SFC)
Hold time, DSF after CAS low
tCFH
20
th(RA)
Hold time, row address after RAS low
tRAH
15
th(TRG)
Hold time, TRG after RAS low
tTLH
15
th(SE)
Hold time, SE after RAS low with TRG = W = low (see Note 13)
tREH
15
th(RWM) Hold time, write mask, transfer enable after RAS low
tRWH
15
th(RDQ)
Hold time, DQ after RAS low (write-mask operation)
tMH
15
th(SFR)
Hold time, DSF after RAS low
tRFH
15
th(RLCA) Hold time, column address after RAS low (see Note 14)
tAR
45
th(CLD)
Hold time, data after CAS low
tDH
20
th(RLD)
Hold time, data after RAS low (see Note 14)
tDHR
45
th(WLD)
Hold time, data after W low
tDH
20
th(CHrd)
Hold time, read after CAS high (see Note 15)
tRCH
0
th(RHrd)
Hold time, read after RAS high (see Note 15)
tRRH
10
th(CLW)
Hold time, write after CAS low
tWCH
30
th(RLW)
Hold time, write after RAS low (see Note 14)
tWCR
50
th(WLG)
Hold time, TRG after W low (see Note 16)
tOEH
25
th(SDS)
Hold time, SDQ after SC high
tSDH
5
th(SHSQ) Hold time, SDQ after SC high
tSOH
5
th(RSF)
Hold time, DSF after RAS low
tFHR
45
th(SCSE) Hold time, serial-write disable
tSWIH
20
td(RLCH) Delay time, RAS low to CAS high
tCSH
100
td(CHRL) Delay time, CAS high to RAS low
tCRP
0
td(CLRH) Delay time, CAS low to RAS high
tRSH
25
td(CLWL) Delay time, CAS low to W low (see Notes 17 and 18)
tCWD
55
td(RLCL) Delay time, RAS low to CAS low (see Note 19)
tRCD
25
75
td(CARH) Delay time, column address to RAS high
tRAL
50
td(RLWL) Delay time, RAS low to W low (see Note 17)
tRWD
130
td(CAWL) Delay time, column address to W low (see Note 17)
tAWD
85
† _{Timing measurements are referenced to VIL max and VIH min.}
NOTES: 13. Register-to-memory (write) transfer cycles only
14. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
15. Either th(RHrd) or t(CHrd) must be satisfied for a read cycle.
16. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle.
17. Read-modify-write operation only
18. TRG must disable the output buffers prior to applying data to the DQ terminals.
19. The maximum value is specified only to assure RAS access time.
’44C251B - 12
MIN MAX
30
30
0
20
20
15
15
15
15
15
15
45
25
50
25
0
10
35
55
30
5
5
45
20
120
0
30
65
25
90
60
155
100
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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