SMJ44C251 Datasheet, PDF (11/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

block write cycle (continued)
Load-Color-Register Cycle
RAS
Block-Write Cycle†
(no DQ mask)
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
Block-Write Cycle†
(load and use DQ mask)
Block-Write Cycle†
(use previously
loaded DQ mask)
CAS
A0 – A8
1
W†
2
3
2
3
2
3
TRG
DSF
DQ0 – DQ3
4
5
6
5
5
† _{W must be low during the block-write cycle.}
NOTE: DQ0 – DQ3 are latched on the later of W or CAS falling edge except in block 6 (see legend).
Legend:
1. Refresh address
2. Row address
3. Block address (A2 – A8)
4. Color-register data
5. Column-mask data
6. DQ-mask data. DQ0 – DQ3 are latched on the falling edge of RAS.
= don’t care
Figure 2. Example Block-Write Diagram Operations
Load Write
Mask
N
I/O3
I/O2
I/O1
I/O0
N+1
N+2
N+3
Block-Write
Enable
A2 – A8
4-of-512
Decode
DQ
Load
Color
Register
Color
Register
Block-Write
Enable
Write-Mask
Register
Write
Enable
Data
In
MUX
Write
Select
Write
Select
Write
Select
Write
Select
MUX
MUX
MUX
MUX
Figure 3. Block-Write Circuit Block Diagram
A0 – A1
1-of- 4
Decode
DQ0
DQ1
DQ2
DQ3
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