OMAPL137DZKB3 Datasheet, PDF (9/223 Pages) Texas Instruments – OMAP-L137 Low-Power Applications Processor

OMAP-L137
www.ti.com
2 Device Overview
SPRS563F – SEPTEMBER 2008 – REVISED FEBRUARY 2013
2.1 Device Characteristics
Table 2-1 provides an overview of the OMAP-L137 low power applications processor. The table shows
significant features of the device, including the capacity of on-chip RAM, peripherals, and the package
type with pin count.
Table 2-1. Characteristics of the OMAP-L137 Processor
HARDWARE FEATURES
EMIFB
EMIFA
Flash Card Interface
EDMA3
Timers
UART
SPI
I²C
Peripherals
Multichannel Audio
Serial Port [McASP]
Not all peripherals pins
are available at the ^{10/100 Ethernet MAC}
same time (for more ^{with Management Data}
detail, see the Device ^I/O
Configurations section). _eHRPWM
eCAP
eQEP
UHPI
USB 2.0 (USB0)
USB 1.1 (USB1)
General-Purpose
Input/Output Port
LCD Controller
PRU Subsystem
(PRUSS)
Size (Bytes)
On-Chip Memory
Organization
OMAP-L137
16/32bit, up to 256MB SDRAM
Asynchronous (8/16-bit bus width) RAM, Flash, 16bit up to 128MB SDRAM, NOR,
NAND
MMC and SD cards supported.
32 independent channels, 8 QDMA channels, 2 Transfer controllers
2 64-Bit General Purpose (each configurable as 2 separate 32-bit timers, 1 configurable
as Watch Dog)
3 (one with RTS and CTS flow control)
2 (each with one hardware chip select)
2 (both Master/Slave)
3 (each with transmit/receive, FIFO buffer, 16/12/4 serializers)
1 (RMII Interface)
6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs
2 32-bit QEP channels with 4 inputs/channel
1 (16-bit multiplexed address/data)
High-Speed OTG Controller with on-chip OTG PHY
Full-Speed OHCI (as host) with on-chip PHY
8 banks of 16-bit
1
2 Programmable PRU Cores
488KB RAM
DSP
32KB L1 Program (L1P)/Cache (up to 32KB)
32KB L1 Data (L1D)/Cache (up to 32KB)
256KB Unified Mapped RAM/Cache (L2)
DSP Memories can be made accessible to ARM, EDMA3, and other peripherals.
ARM
16KB I-Cache
16KB D-Cache
8KB RAM (Vector Table)
64KB ROM
C674x CPU ID + CPU
Rev ID
C674x Megamodule
Revision
Control Status Register
(CSR.[31:16])
Revision ID Register
(MM_REVID[15:0])
JTAG BSDL_ID
DEVIDR0 register
ADDITIONAL SHARED MEMORY
128KB RAM
0x1400
0x0000
0x0B7D F02F (Silicon Revision 1.0)
0x8B7D F02F (Silicon Revision 1.1)
0x9B7D F02F (Silicon Revisions 3.0, 2.1, and 2.0)
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Device Overview
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