OMAPL137DZKB3 Datasheet, PDF (143/223 Pages) Texas Instruments – OMAP-L137 Low-Power Applications Processor

OMAP-L137
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SPRS563F – SEPTEMBER 2008 – REVISED FEBRUARY 2013
Table 5-69. Additional⁽¹⁾ SPI1 Slave Timings, 4-Pin Enable Option^{(2) (3)}
No.
PARAMETER
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Delay from final
24
t_{d(SPC_ENAH)S}
SPI1_CLK edge to
slave deasserting
SPI1_ENA.
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
MIN
1.5 P -3
MAX
UNIT
2.5 P + 19
– 0.5t_c(SPC)M + 1.5 P -3 – 0.5t_c(SPC)M + 2.5 P + 19
ns
1.5 P -3
2.5 P + 19
– 0.5t_c(SPC)M + 1.5 P -3 – 0.5t_c(SPC)M + 2.5 P + 19
(1) These parameters are in addition to the general timings for SPI slave modes (Table 5-65).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 5-70. Additional⁽¹⁾ SPI1 Slave Timings, 4-Pin Chip Select Option^{(2) (3)}
No.
25 t_{d(SCSL_SPC)S}
26 t_{d(SPC_SCSH)S}
27 t_{ena(SCSL_SOMI)S}
28 t_{dis(SCSH_SOMI)S}
PARAMETER
Required delay from SPI1_SCS asserted at slave to first
SPI1_CLK edge at slave.
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Required delay from final
SPI1_CLK edge before
SPI1_SCS is deasserted.
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Delay from master asserting SPI1_SCS to slave driving
SPI1_SOMI valid
Delay from master deasserting SPI1_SCS to slave 3-stating
SPI1_SOMI
MIN
2P
0.5t_c(SPC)M + P + 5
P+5
0.5t_c(SPC)M + P + 5
P+5
MAX
UNIT
ns
ns
P + 19 ns
P + 19 ns
(1) These parameters are in addition to the general timings for SPI slave modes (Table 5-65).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
No.
25 t_{d(SCSL_SPC)S}
26 t_{d(SPC_SCSH)S}
27 t_{ena(SCSL_SOMI)S}
28 t_{dis(SCSH_SOMI)S}
29 t_{ena(SCSL_ENA)S}
Table 5-71. Additional⁽¹⁾ SPI1 Slave Timings, 5-Pin Option^{(2) (3)}
PARAMETER
Required delay from SPI1_SCS asserted at slave to first
SPI1_CLK edge at slave.
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Required delay from final SPI1_CLK
edge before SPI1_SCS is
deasserted.
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Delay from master asserting SPI1_SCS to slave driving
SPI1_SOMI valid
Delay from master deasserting SPI1_SCS to slave 3-stating
SPI1_SOMI
Delay from master deasserting SPI1_SCS to slave driving
SPI1_ENA valid
MIN
2P
0.5t_c(SPC)M + P +
5
P+5
0.5t_c(SPC)M + P +
5
P+5
MAX
UNIT
ns
ns
P + 19 ns
P + 19 ns
19 ns
(1) These parameters are in addition to the general timings for SPI slave modes (Table 5-65).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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Peripheral Information and Electrical Specifications 143
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