OMAPL137DZKB3 Datasheet, PDF (193/223 Pages) Texas Instruments – OMAP-L137 Low-Power Applications Processor

OMAP-L137
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SPRS563F – SEPTEMBER 2008 – REVISED FEBRUARY 2013
Table 5-102. Switching Characteristics for Host-Port Interface Cycles^{(1) (2) (3)}
No.
PARAMETER
MIN MAX UNIT
For HPI Write, UHPI_HRDY can go high (not
ready) for these HPI Write conditions;
otherwise, UHPI_HRDY stays low (ready):
Case 1: Back-to-back HPIA writes (can be
either first or second half-word)
Case 2: HPIA write following a PREFETCH
command (can be either first or second half-
word)
Case 3: HPID write when FIFO is full or
flushing (can be either first or second half-
word)
Case 4: HPIA write and Write FIFO not empty
5
t_{d(HSTBL-HRDYV)}
5a t_{d(HASL-HRDYV)}
6
t_{en(HSTBL-HDLZ)}
7
t_d(HRDYL-HDV)
8
t_{oh(HSTBH-HDV)}
14 t_{dis(HSTBH-HDHZ)}
15 t_d(HSTBL-HDV)
18 t_{d(HSTBH-HRDYV)}
Delay time,
UHPI_HSTROBE low to
UHPI_HRDY valid
For HPI Read, UHPI_HRDY can go high (not
ready) for these HPI Read conditions:
Case 1: HPID read (with auto-increment) and
data not in Read FIFO (can only happen to
first half-word of HPID access)
Case 2: First half-word access of HPID Read
without auto-increment
For HPI Read, UHPI_HRDY stays low (ready)
for these HPI Read conditions:
Case 1: HPID read with auto-increment and
data is already in Read FIFO (applies to either
half-word of HPID access)
Case 2: HPID read without auto-increment
and data is already in Read FIFO (always
applies to second half-word of HPID access)
Case 3: HPIC or HPIA read (applies to either
half-word access)
12 ns
Delay time, UHPI_HAS low to UHPI_HRDY valid
13
Enable time, HD driven from UHPI_HSTROBE low
2
ns
Delay time, UHPI_HRDY low to HD valid
0
ns
Output hold time, HD valid after UHPI_HSTROBE high
1.5
ns
Disable time, HD high-impedance from UHPI_ HSTROBE high
12 ns
Delay time,
UHPI_HSTROBE low to HD valid
For HPI Read. Applies to conditions where
data is already residing in HPID/FIFO:
Case 1: HPIC or HPIA read
Case 2: First half-word of HPID read with
auto-increment and data is already in Read
FIFO
Case 3: Second half-word of HPID read with
or without auto-increment
15 ns
Delay time,
UHPI_HSTROBE high to
UHPI_HRDY valid
For HPI Write, UHPI_HRDY can go high (not
ready) for these HPI Write conditions;
otherwise, UHPI_HRDY stays low (ready):
Case 1: HPID write when Write FIFO is full
(can happen to either half-word)
Case 2: HPIA write (can happen to either half-
word)
Case 3: HPID write without auto-increment
(only happens to second half-word)
12 ns
(1) M=SYSCLK2 period (CPU clock frequency)/2 in ns.
(2) UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR
UHPI_HDS2)] OR UHPI_HCS.
(3) By design, whenever UHPI_HCS is driven inactive (high), HPI will drive UHPI_HRDY active (low).
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Peripheral Information and Electrical Specifications 193
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