OMAPL137DZKB3 Datasheet, PDF (1/223 Pages) Texas Instruments – OMAP-L137 Low-Power Applications Processor

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SPRS563F – SEPTEMBER 2008 – REVISED FEBRUARY 2013
OMAP-L137 Low-Power Applications Processor
Check for Samples: OMAP-L137
1 OMAP-L137 Low-Power Applications Processor
1.1 Features
1234
• Highlights
– 8K-Byte RAM (Vector Table)
– Dual Core SoC
– 64K-Byte ROM
• 375/456-MHz ARM926EJ-S™ RISC MPU
• C674x Instruction Set Features
• 375/456-MHz C674x VLIW DSP
– Superset of the C67x+™ and C64x+™ ISAs
– TMS320C674x Fixed/Floating-Point VLIW
– Up to 3648/2736 C674x MIPS/MFLOPS
DSP Core
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– Enhanced Direct-Memory-Access Controller
– 8-Bit Overflow Protection
3 (EDMA3)
– Bit-Field Extract, Set, Clear
– 128K-Byte RAM Shared Memory
– Normalization, Saturation, Bit-Counting
– Two External Memory Interfaces
– Compact 16-Bit Instructions
– Three Configurable 16550 type UART
Modules
– LCD Controller
– Two Serial Peripheral Interfaces (SPI)
– Multimedia Card (MMC)/Secure Digital (SD)
– Two Master/Slave Inter-Integrated Circuit
– One Host-Port Interface (HPI)
• C674x Two Level Cache Memory Architecture
– 32K-Byte L1P Program RAM/Cache
– 32K-Byte L1D Data RAM/Cache
– 256K-Byte L2 Unified Mapped RAM/Cache
– Flexible RAM/Cache Partition (L1 and L2)
• Enhanced Direct-Memory-Access Controller 3
(EDMA3):
– USB 1.1 OHCI (Host) With Integrated PHY
(USB1)
• Applications
– Industrial Diagnostics
– Test and measurement
– Military Sonar/ Radar
– 2 Transfer Controllers
– 32 Independent DMA Channels
– 8 Quick DMA Channels
– Programmable Transfer Burst Size
• TMS320C674x Fixed/Floating-Point VLIW DSP
Core
– Medical measurement
– Load-Store Architecture With Non-Aligned
– Professional Audio
Support
• Software Support
– 64 General-Purpose Registers (32 Bit)
– TI DSP/BIOS™
– Six ALU (32-/40-Bit) Functional Units
– Chip Support Library and DSP Library
• Supports 32-Bit Integer, SP (IEEE Single
• Dual Core SoC
– 375/456-MHz ARM926EJ-S™ RISC MPU
– 375/456-MHz C674x VLIW DSP
• ARM926EJ-S Core
– 32-Bit and 16-Bit (Thumb®) Instructions
– DSP Instruction Extensions
– Single Cycle MAC
– ARM™ Jazelle® Technology
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
• Supports up to Four SP Additions Per
Clock, Four DP Additions Every 2 Clocks
• Supports up to Two Floating Point (SP or
DP) Reciprocal Approximation (RCPxP)
and Square-Root Reciprocal
Approximation (RSQRxP) Operations Per
Cycle
– EmbeddedICE-RT™ for Real-Time Debug
– Two Multiply Functional Units
• ARM9 Memory Architecture
• Mixed-Precision IEEE Floating Point
– 16K-Byte Instruction Cache
Multiply Supported up to:
– 16K-Byte Data Cache
– 2 SP x SP -> SP Per Clock
– 2 SP x SP -> DP Every Two Clocks
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DSP/BIOS, TMS320C6000, C6000 are trademarks of Texas Instruments.
2
ARM926EJ-S, ETM9, CoreSight are trademarks of ARM Limited.
3
All other trademarks are the property of their respective owners.
4
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated