OMAPL137DZKB3 Datasheet, PDF (70/223 Pages) Texas Instruments – OMAP-L137 Low-Power Applications Processor

OMAP-L137
SPRS563F – SEPTEMBER 2008 – REVISED FEBRUARY 2013
www.ti.com
5.8.1.3 AINTC Hardware Interrupt Nesting Support
Interrupt nesting occurs when an interrupt service routine re-enables interrupts, to allow the CPU to
interrupt the ISR if a higher priority event occurs. The AINTC provides hardware support to facilitate
interrupt nesting. It supports both global and per host interrupt (FIQ and IRQ in this case) automatic
nesting. If enabled, the AINTC will automatically update an internal nesting register that temporarily masks
interrupts at and below the priority of the current interrupt channel. Then if the ISR re-enables interrupts;
only higher priority channels will be able to interrupt it. The nesting level is restored by the ISR by writing
to the nesting level register on completion. Support for nesting can be enabled/disabled by software, with
the option of automatic nesting on a global or per host interrupt basis; or manual nesting.
5.8.1.4 AINTC System Interrupt Assignments on OMAP-L137
System Interrupt assignments for the OMAP-L137 are listed in Table 5-7
SYSTEM INTERRUPT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Table 5-7. AINTC System Interrupt Assignments
INTERRUPT NAME
COMMTX
COMMRX
NINT
PRU_EVTOUT0
PRU_EVTOUT1
PRU_EVTOUT2
PRU_EVTOUT3
PRU_EVTOUT4
PRU_EVTOUT5
PRU_EVTOUT6
PRU_EVTOUT7
EDMA3_CC0_CCINT
EDMA3_CC0_CCERRINT
EDMA3_TC0_TCERRINT
EMIFA_INT
IIC0_INT
MMCSD_INT0
MMCSD_INT1
PSC0_ALLINT
RTC_IRQS[1:0]
SPI0_INT
T64P0_TINT12
T64P0_TINT34
T64P1_TINT12
T64P1_TINT34
UART0_INT
-
MPU_BOOTCFG_ERR
SYSCFG_CHIPINT0
SYSCFG_CHIPINT1
SYSCFG_CHIPINT2
SYSCFG_CHIPINT3
EDMA3_TC1_TCERRINT
EMAC_C0RXTHRESH
SOURCE
ARM
ARM
ARM
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
EDMA Channel Controller Region 0
EDMA Channel Controller
EDMA Transfer Controller 0
EMIFA
I2C0
MMCSD
MMCSD
PSC0
RTC
SPI0
Timer64P0 Interrupt 12
Timer64P0 Interrupt 34
Timer64P1 Interrupt 12
Timer64P1 Interrupt 34
UART0
Reserved
Shared MPU and SYSCFG Address/Protection Error
Interrupt
SYSCFG CHIPSIG Register
SYSCFG CHIPSIG Register
SYSCFG CHIPSIG Register
SYSCFG CHIPSIG Register
EDMA Transfer Controller 1
EMAC - Core 0 Receive Threshold Interrupt
70
Peripheral Information and Electrical Specifications
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