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DAC8734_091 Datasheet, PDF (9/41 Pages) Texas Instruments – Quad, 16-Bit, High-Accuracy, ±16V Output, Serial Input DIGITAL-TO-ANALOG CONVERTER
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DAC8734
www.ti.com .................................................................................................................................................. SBAS465A – MAY 2009 – REVISED SEPTEMBER 2009
TIMING DIAGRAMS
Case 1: Stand-alone mode, LDAC tied low.
t8
t4
CS
SCLK
SDI
t1
t3
t2
t5
t6
tR
tF
BIT 23 (MSB)
BIT 22
Input Data Register and
t7
DAC Latch Updated(1)
BIT 1
BIT 0
Low
LDAC
Case 2: Stand-alone mode, LDAC active high.
t8
t4
CS
SCLK
SDI
t1
t3
t2
t5
t6
tR
tF
BIT 23 (MSB)
BIT 22
Input Data Register Updated
t7
but DAC Latch is Not Updated
BIT 1
BIT 0
LDAC
High
Input Word To Write the Data to the Selected DAC
t9
t10
= Don’t Care
Bit 23 = MSB
Bit 0 = LSB
DAC Latch Updated
Figure 1. SPI Timing for Stand-Alone Mode
TIMING CHARACTERISTICS For Figure 1(1)(2)(3)
At TA = –40°C to +105°C, unless otherwise noted.
PARAMETER
2.7V ≤ DVDD ≤ 5.5V,
IOVDD = 1.8V
MIN
MAX
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Clock frequency
SCLK cycle time
SCLK high time
SCLK low time
CS falling edge to SCLK falling edge(4)
Input data setup time
Input data hold time
SCLK falling edge to CS rising edge
CS high time
CS rising edge to LDAC falling edge
LDAC pulse width
RST pulse width
30
33
16
16
11
5
5
15
60
30
25
25
2.7V ≤ DVDD ≤ 3.6V,
2.7V ≤ IOVDD ≤ DVDD
MIN
MAX
40
25
12
12
9
5
5
12
50
25
20
20
3.6V < DVDD ≤ 5.5V,
2.7V ≤ IOVDD ≤ DVDD
MIN
MAX
50
20
10
10
7
5
5
10
30
20
15
15
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) Specified by design and characterization.
(2) Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
(3) All input signals are specified with tR = tF = 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2.
(4) The first SCLK edge after CS goes low must be a falling edge.
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC8734
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