DAC8734_091 Datasheet, PDF (23/41 Pages) Texas Instruments – Quad, 16-Bit, High-Accuracy, ±16V Output, Serial Input DIGITAL-TO-ANALOG CONVERTER

DAC8734
www.ti.com .................................................................................................................................................. SBAS465A – MAY 2009 – REVISED SEPTEMBER 2009
SERIAL INTERFACE
The DAC8734 is controlled over a versatile, three-wire serial interface that operates at clock rates of up to
50MHz and is compatible with SPI, QSPI™, Microwire™, and DSP™ standards.
SPI Shift Register
The SPI Shift Register is 24 bits wide. Data are loaded into the device MSB first as a 24-bit word under the
control of the serial clock input, SCLK. The falling edge of CS starts the communication cycle. Data are latched
into the SPI Shift Register on the falling edge of SCLK while CS is low. When CS is high, SCLK is blocked, SDI
is ignored, and the SDO line is in a high-impedance state. The contents of the SPI Shift Register are loaded into
the addressed internal register on the rising edge of CS. The SPI Shift Register consists of a read/write bit, four
register address bits, 16 data bits, and three reserved bits, as shown in Table 2. The timing for this operation is
shown in the Timing Diagrams section. When the device is loaded, the command is decoded, and the new data
are transferred into the proper data registers.
The serial interface works with both continuous and non-continuous serial clocks. A continuous SCLK source can
only be used if CS is held low for the correct number of clock cycles. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used and CS must be taken high after the final clock in
order to latch the data.
Stand-Alone Operation
The first falling edge of CS starts the operation cycle. Exactly 24 falling clock edges must be applied before CS is
brought back high again. If CS is brought high before the 24th falling SCLK edge, then the data are ignored. If
more than 24 falling SCLK edges are applied before CS is brought high, then the last 24 bits are considered. The
addressed internal register is updated from the Shift Register on the rising edge of CS. In order for another serial
transfer to take place, CS must be brought low again.
When the data have been transferred into the chosen register of the addressed DAC, all DAC latches and analog
outputs can be updated by taking the LDAC pin low or setting the LD bit in the Command Register.
Daisy-Chain Operation
For systems that contain more than one device, the SDO pin can be used to daisy-chain multiple devices
together. Daisy-chain operation can be useful in system diagnostics and in reducing the number of serial
interface lines. Note that before daisy-chain operation can begin, the SDO pin must be enabled by clearing the
SDO disable bit in the Command Register (DSDO = '0'). By default, this bit is cleared after power-on or reset.
The first falling edge of CS starts the operation cycle. SCLK is continuously applied to the input shift register
when CS is low. If more than 24 clock pulses are applied, the data ripple out of the shift register and appear on
the SDO line. These data are clocked out on the rising edge of SCLK and are valid on the falling edge. By
connecting the SDO output of the first device to the SDI input of the next device in the chain, a multiple-device
interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock
cycles must equal 24 × N, where N is the total number of DAC8734s in the chain. When the serial transfer to all
devices is complete, CS is taken high. This action latches data from the SPI shift register into the device input
register of each device in the daisy-chain, and prevents any further data from being clocked in.
Copyright © 2009, Texas Instruments Incorporated
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