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DAC8734_091 Datasheet, PDF (11/41 Pages) Texas Instruments – Quad, 16-Bit, High-Accuracy, ±16V Output, Serial Input DIGITAL-TO-ANALOG CONVERTER
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DAC8734
www.ti.com .................................................................................................................................................. SBAS465A – MAY 2009 – REVISED SEPTEMBER 2009
Case 5: Readback for Stand-alone mode.
t8
t4
t7
CS
SCLK
SDI
t1
t2
t3
t5
t6
BIT 23
tR
tF
BIT 22
BIT 0
Input Word Specifies Register to be Read
SDO
Low
LDAC
Input Data Register Updated
BIT 23
BIT 22
BIT 1
BIT 0
t13
t11
BIT 23
t12
BIT 22
Write NOP Command
BIT 1
BIT 0
Data from the Selected Register
= Don’t Care
Bit 23 = MSB
Bit 0 = LSB
Figure 3. SPI Timing for Readback Operation in Stand-Alone Mode
TIMING CHARACTERISTICS For Figure 2 to Figure 3(1)(2)(3)
At TA = –40°C to +105°C, unless otherwise noted.
PARAMETER
2.7V ≤ DVDD ≤ 5.5V,
IOVDD = 1.8V
MIN
MAX
2.7V ≤ DVDD ≤ 3.6V,
2.7V ≤ IOVDD ≤ DVDD
MIN
MAX
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
Clock frequency
SCLK cycle time
SCLK high time
SCLK low time
CS falling edge to SCLK falling edge(4)
Input data setup time
Input data hold time
SCLK falling edge to CS rising edge
CS high time
CS rising edge to LDAC falling edge
LDAC pulse width
SDO data valid from SCLK rising edge
SDO data hold time from SCLK falling
edge
15
20
66
50
33
25
33
25
25
22
5
5
5
5
15
12
60
50
30
25
25
20
25
20
30
25
t13
SDO data valid from CS falling edge
RST pulse width
20
17
25
20
3.6V < DVDD ≤ 5.5V,
2.7V ≤ IOVDD ≤ DVDD
MIN
MAX
25
40
20
20
17
5
5
10
30
20
15
15
20
12
15
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) Specified by design and characterization.
(2) Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
(3) All input signals are specified with tR = tF = 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2.
(4) The first SCLK edge after CS goes low must be a falling edge.
Copyright © 2009, Texas Instruments Incorporated
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