DAC8734_091 Datasheet, PDF (21/41 Pages) Texas Instruments – Quad, 16-Bit, High-Accuracy, ±16V Output, Serial Input DIGITAL-TO-ANALOG CONVERTER

DAC8734
www.ti.com .................................................................................................................................................. SBAS465A – MAY 2009 – REVISED SEPTEMBER 2009
UPDATING THE DAC OUTPUTS
The DAC8734 has a double-buffered interface that consists of two register banks for every channel: the input
register and the DAC latch. The digital code is transferred from the SPI shift register to the addressed channel
input register upon completion of a valid write sequence. The DAC latch contains the digital code used by the
resistor R-2R ladder. The contents of the DAC latch define the output from the DAC. The DAC outputs can be
updated individually or simultaneously. The DAC8734 updates the DAC latch only if it has been accessed since
the last time the LDAC pin was brought low or the LD bit in the Command Register was set to '1', thereby
eliminating any unnecessary glitch. The DAC channels that were not accessed are not reloaded, and the output
values remain unchanged.
Individual DAC Channel Update
In this mode, the LDAC pin is held low while the CS pin is low and the data are clocked into the SPI shift register.
At the end of the data transfer into the shift register, the CS pin is brought high. This action updates both the
addressed input data register and the corresponding DAC latch register. The DAC latch register controls the
R-2R switches; thus, an update on the DAC latch register updates the corresponding DAC channel analog
output.
Simultaneous Update of Multiple DAC Channels
In this mode, the LDAC pin is held high while the CS pin is low and data are clocked into the SPI shift register. At
the end of the data transfer into the shift register, the CS pin is brought high. This action updates only the
addressed input data register; it does not update the DAC latch register or change the output. The DAC latch and
the analog output are updated only when the LDAC pin goes low, or when the LD bit in the Command Register is
set to '1' at anytime after the input data register is written.
HARDWARE RESET
When the RST pin is low, the device is in hardware reset. All the analog outputs (V_OUT-0 to V_OUT-3), the input
registers, and the DAC latches are set to the reset values shown in Table 1. All registers are loaded with default
values. Communication is disabled, and the signals on the SDI, CS, and SCLK pins are ignored. On the rising
edge of the RST pin, the analog outputs (V_OUT-0 to V_OUT-3) maintain the reset value (0V) until a new value is
programmed. After the RST pin goes high, the device returns to normal operation. Note that the default values of
the gain bits in the Command Register are '1' after a reset. For gain = 2, the gain bits must be cleared to '0'.
Table 1. Reset Values
UNI/BIP PIN
DGND
IOV_DD
OUTPUT MODE
Bipolar
Unipolar
INPUT FORMAT
Twos Complement
Straight Binary
VALUE OF INPUT REGISTER
AND DAC LATCH
0000h
0000h
V_OUT
0V
0V
Setting the RST bit in the Command Register to '1' performs a software reset, which is functionally the same as a
hardware reset. After reset completes, the RST bit returns to '0' automatically.
POWER-ON RESET
On power-on, the input data registers and DAC latches are loaded with the value defined by the UNI/BIP pins
(see Table 1). All other registers are loaded with default values. After power-on, the outputs of the V_OUT pins are
set to 0V.
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC8734
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