English
Language : 

DAC8734_091 Datasheet, PDF (19/41 Pages) Texas Instruments – Quad, 16-Bit, High-Accuracy, ±16V Output, Serial Input DIGITAL-TO-ANALOG CONVERTER
◁
DAC8734
www.ti.com .................................................................................................................................................. SBAS465A – MAY 2009 – REVISED SEPTEMBER 2009
THEORY OF OPERATION
DAC ARCHITECTURE
The DAC8734 is a highly-integrated, quad-channel, 16-bit, voltage-output DAC with internal reference buffers
and output buffers. Each channel consists of an R-2R ladder configuration with the three MSBs segmented,
followed by an operational amplifier, as shown in Figure 41. The DAC8734 has a high-impedance, buffered
reference input; the output of the reference buffers drives the R-2R ladders. The output buffer is designed to
allow user-configurable adjustments, giving the DAC8734 four different output voltage range settings. With the
production trim process, this device has excellent dc accuracy and ac performance.
From Reference
Buffer Output
R
R
R
R
2R
2R
2R
2R
2R
2R
2R
2R
2R
S19 S18
S14 S13
S12
S11
S10
S0
RFB
VOUT
Three MSBs Decoded Into
Seven Equal Segments
13-Bit R-2R Ladder
Figure 41. DAC8734 Architecture
SGND
CHANNEL GROUPS
The four DAC channels are arranged into two groups (A and B) with two channels per group. Group A consists
of DAC-0 and DAC-1, and Group B consists of DAC-2 and DAC-3. The two DAC channels of Group A derive
their reference voltage from REF-A, and those of Group B from REF-B.
USER-CALIBRATION FOR ZERO ERROR AND GAIN ERROR
The DAC8734 implements a user-calibration function that allows for trimming the system gain and zero errors.
Each DAC channel has a Gain Register and Zero Register and the DAC output is calibrated according to the
value of the corresponding registers. The range of gain adjustment is typically ±0.195% of full-scale with 1 LSB
per step. The zero code adjustment is typically ±0.0488% of full-scale with 0.125 LSB per step. The input data
format of the Gain and Zero registers is twos complement. Refer to Table 9 and Table 10 for more details.
If the system-level calibration is not needed, these registers should be left at the respective default values
(0000h) at power-on.
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC8734
Submit Documentation Feedback
19
 ▷