DAC8734_091 Datasheet, PDF (25/41 Pages) Texas Instruments – Quad, 16-Bit, High-Accuracy, ±16V Output, Serial Input DIGITAL-TO-ANALOG CONVERTER

DAC8734
www.ti.com .................................................................................................................................................. SBAS465A – MAY 2009 – REVISED SEPTEMBER 2009
SPI SHIFT REGISTER
The SPI Shift Register is 24 bits wide, as shown in Table 2. By default, the SPI shift register resets to 000000h at
power-on or after a reset.
MSB
DB23
R/W
DB22
0
DB21
0
Table 2. SPI Shift Register Format
DB20
0
DB19
A3
DB18
A2
DB17
A1
DB16
A0
DB15:DB0
DATA
R/W—Indicates a read from or a write to the addressed register.
R/W = '0' sets a write operation and the data are written to the specified register.
R/W = '1' sets a read-back operation. For read operation, bits A3 to A0 select the register to be read. The
remaining are don’t care bits. During the next SPI operation, the data appearing on SDO pin are from the
previously addressed register.
[A3:A0]—Address bits that specify which register is accessed.
DATA—16 data bits
All DAC8734 registers (command registers and data registers) are 16-bit. Table 3 shows the register map.
Table 3. Register Map
ADDRESS BITS
A3 A2 A1 A0
0000
0001
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Others
DB15
A/B
MDAC-3
DB14
LD
MDAC-2
DB13 DB12 DB11
RST
PD-A PD-B
MDAC-1 MDAC-0 AIN
Reserved ⁽¹⁾
Reserved ⁽¹⁾
Reserved ⁽¹⁾
Reserved ⁽¹⁾
Reserved ⁽¹⁾
Reserved ⁽¹⁾
Reserved ⁽¹⁾
Reserved ⁽¹⁾
DATA BITS
DB10 DB9
DB8
DB7
DB6
DB5:
DB2
Rsvd⁽¹⁾ GPIO-1 GPIO-0 DSDO NOP
Reserved ⁽¹⁾
GAIN
Bits
D15:D0
D15:D0
D15:D0
D15:D0
Z8:Z0
Z8:Z0
Z8:Z0
Z8:Z0
G7:G0
G7:G0
G7:G0
G7:G0
Reserved ⁽¹⁾
DB1:
DB0
Rsvd ⁽¹⁾
REGISTER
Command
Register
Monitor Register
DAC-0
DAC-1
DAC-2
DAC-3
Zero Register-0
Zero Register-1
Zero Register-2
Zero Register-3
Gain Register-0
Gain Register-1
Gain Register-2
Gain Register-3
—
(1) Writing to a reserved bit has no effect; reading the bit returns '0'.
Copyright © 2009, Texas Instruments Incorporated
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