DAC8734_091 Datasheet, PDF(22/41 Page) Texas Instruments – Quad, 16-Bit, High-Accuracy, ±16V Output, Serial Input DIGITAL-TO-ANALOG CONVERTER

◁

DAC8734

SBAS465A â MAY 2009 â REVISED SEPTEMBER 2009 .................................................................................................................................................. www.ti.com

ANALOG OUTPUT MONITOR PIN (VMON)

The VMON pin is the analog output monitor. The analog output monitor function consists of an analog multiplexer

addressed via the serial interface, allowing one of the four channel outputs or the AIN input to be routed to this

pin for monitoring. The monitor function is controlled by the Monitor Register, which allows the monitored output

to be enabled or disabled. When all multiplexer channels are disabled, the monitor output is high impedance;

therefore, several monitor outputs can be connected in parallel with only one enabled at a time. Table 5 shows

the settings relevant to the monitor function.

Note that the multiplexer is implemented as a series of analog switches. Care should be taken to ensure the

maximum current from the VMON pin must not be greater than the given specification because such a condition

could conceivably cause a large amount of current to flow from the input of the multiplexer (that is, from VOUT-x

or AIN) to the output of the multiplexer (VMON). Also, the VMON pin output impedance is approximately 2.2kâ¦;

therefore, VMON should be measured with a high-impedance input.

POWER-DOWN MODE

The DAC8734 implements a group power-down feature to reduce power consumption in case some channels

are idle. When the power-down bit (PD-A and/or PD-B) in the Command Register is set to '1', the corresponding

group goes into a power-down state. During power-down, the reference buffer and output buffers of that group

are powered down and the corresponding analog outputs are set to 0V through an internal 10kâ¦ resistor to

AGND. The contents of the internal registers do not change, and the bus interface remains active in order to

continue communication and receive commands from the host controller. Any internal register can be read from

or written to. The host controller can wake the device from power-down mode and return to normal operating

mode by clearing the power-down bit (PD-A and/or PD-B) in the Command Register. Recovery completes in

approximately 50Âµs.

POWER-SUPPLY SEQUENCING

In order to ensure proper initialization of the DAC8734, the digital supplies (DVDD and IOVDD) and logic inputs

(UNI/BIP-x) must be applied before AVSS and AVDD. Additionally, AVSS must be applied before AVDD unless both

can ramp up at the same time. REF-x should be applied after AVDD comes up in order to make sure the ESD

protection circuitry does not turn on.

GENERAL-PURPOSE INPUT/OUTPUT PINS (GPIO-0, -1)

The GPIO-0 and GPIO-1 pins are general-purpose, bidirectional, digital input/output (I/O) signals, as Figure 42

shows. These pins can receive an input or produce an output. When the GPIO-n pin acts as an output, it has an

open-drain, and the status is determined by the corresponding GPIO-n bit of the Command Register. The output

status is high impedance when the GPIO-n bit is set to '1', and is logic low when the GPIO-n bit is cleared ('0').

Note that a 10kâ¦ pullup resistor is required when using the GPIO-n pin as an output.

To use the GPIO-n pin as an input, the GPIO-n bits in the Command Register must be set to '1'. When the

GPIO-n pin acts as input, the digital value on the pin is acquired by reading the GPIO-n bit.

After a power-on reset or any forced hardware or software reset, all GPIO-n bits are set to '1', and the GPIO-n

pin goes to a high-impedance state.

Bit GPIO-x (when writing)

GPIO-x

Enable

Bit GPIO-x (when reading)

Submit Documentation Feedback

Figure 42. GPIO Pins

Product Folder Link(s): DAC8734

▷