OMAP5910 Datasheet, PDF (77/166 Pages) Texas Instruments – DUAL-CORE PROCESSOR

Functional Overview
Table 3−20. System DMA Controller Registers (Continued)
BYTE
ADDRESS
REGISTER NAME
DESCRIPTION
ACCESS ACCESS RESET
WIDTH TYPE
VALUE
FFFE:D958 SYS_DMA_CPC_CH5
Channel 5 Progress Counter Register
16
RW
undef
FFFE:D95A −
FFFE:D97E
Reserved
FFFE:D980 SYS_DMA_CSDP_CH6
Channel 6 Source/Destination Parameters Register
16
RW
0000h
FFFE:D982 SYS_DMA_CCR_CH6
Channel 6 Control Register
16
RW
0000h
FFFE:D984 SYS_DMA_CICR_CH6
Channel 6 Interrupt Control Register
16
RW
0003h
FFFE:D986 SYS_DMA_CSR_CH6
Channel 6 Status Register
16
R
0000h
FFFE:D988 SYS_DMA_CSSA_L_CH6 Channel 6 Source Start Address Register LSB
16
RW
undef
FFFE:D98A SYS_DMA_CSSA_U_CH6 Channel 6 Source Start Address Register MSB
16
RW
undef
FFFE:D98C SYS_DMA_CDSA_L_CH6 Channel 6 Destination Start Address Register LSB
16
RW
undef
FFFE:D98E SYS_DMA_CDSA_U_CH6 Channel 6 Destination Start Address Register MSB
16
RW
undef
FFFE:D990 SYS_DMA_CEN_CH6
Channel 6 Element Number Register
16
RW
undef
FFFE:D992 SYS_DMA_CFN_CH6
Channel 6 Frame Number Register
16
RW
undef
FFFE:D994 SYS_DMA_CFI_CH6
Channel 6 Frame Index Register
16
RW
undef
FFFE:D996 SYS_DMA_CEI_CH6
Channel 6 Element Index Register
16
RW
undef
FFFE:D998 SYS_DMA_CPC_CH6
Channel 6 Progress Counter Register
16
RW
undef
FFFE:D99A −
FFFE:D9BE
Reserved
FFFE:D9C0 SYS_DMA_CSDP_CH7
Channel 7 Source/Destination Parameters Register
16
RW 0000h
FFFE:D9C2 SYS_DMA_CCR_CH7
Channel 7 Control Register
16
RW 0000h
FFFE:D9C4 SYS_DMA_CICR_CH7
Channel 7 Interrupt Control Register
16
RW 0003h
FFFE:D9C6 SYS_DMA_CSR_CH7
Channel 7 Status Register
16
R
0000h
FFFE:D9C8 SYS_DMA_CSSA_L_CH7 Channel 7 Source Start Address Register LSB
16
RW undef
FFFE:D9CA SYS_DMA_CSSA_U_CH7 Channel 7 Source Start Address Register MSB
16
RW undef
FFFE:D9CC SYS_DMA_CDSA_L_CH7 Channel 7 Destination Start Address Register LSB
16
RW undef
FFFE:D9CE SYS_DMA_CDSA_U_CH7 Channel 7 Destination Start Address Register MSB
16
RW undef
FFFE:D9D0 SYS_DMA_CEN_CH7
Channel 7 Element Number Register
16
RW undef
FFFE:D9D2 SYS_DMA_CFN_CH7
Channel 7 Frame Number Register
16
RW undef
FFFE:D9D4 SYS_DMA_CFI_CH7
Channel 7 Frame Index Register
16
RW undef
FFFE:D9D6 SYS_DMA_CEI_CH7
Channel 7 Element Index Register
16
RW undef
FFFE:D9D8 SYS_DMA_CPC_CH7
Channel 7 Progress Counter Register
16
RW undef
FFFE:D9DA −
FFFE:D9FE
Reserved
FFFE:DA00 SYS_DMA_CSDP_CH8
Channel 8 Source/Destination Parameters Register
16
RW 0000h
FFFE:DA02 SYS_DMA_CCR_CH8
Channel 8 Control Register
16
RW 0000h
FFFE:DA04 SYS_DMA_CICR_CH8
Channel 8 Interrupt Control Register
16
RW 0003h
FFFE:DA06 SYS_DMA_CSR_CH8
Channel 8 Status Register
16
R
0000h
FFFE:DA08 SYS_DMA_CSSA_L_CH8 Channel 8 Source Start Address Register LSB
16
RW undef
FFFE:DA0A SYS_DMA_CSSA_U_CH8 Channel 8 Source Start Address Register MSB
16
RW undef
FFFE:DA0C SYS_DMA_CDSA_L_CH8 Channel 8 Destination Start Address Register LSB
16
RW undef
FFFE:DA0E SYS_DMA_CDSA_U_CH8 Channel 8 Destination Start Address Register MSB
16
RW undef
FFFE:DA10 SYS_DMA_CEN_CH8
Channel 8 Element Number Register
16
RW undef
FFFE:DA12 SYS_DMA_CFN_CH8
Channel 8 Frame Number Register
16
RW undef
FFFE:DA14 SYS_DMA_CFI_CH8
Channel 8 Frame Index Register
16
RW undef
August 2002 − Revised August 2004
SPRS197D
77