OMAP5910 Datasheet, PDF (143/166 Pages) Texas Instruments – DUAL-CORE PROCESSOR

Electrical Specifications
Table 5−15. McBSP Switching Characteristics^{†‡§}
NO.
PARAMETER
MIN MAX UNIT
M0 t_{d(CKSH-CKRXH)}
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
McBSP1
CLKR/X int
2
33 ns
M1 t_c(CKRX)
M2 t_w(CKRXH)
M3 t_w(CKRXL)
M4 t_d(CKRH-FRV)
Cycle time, CLKR/X
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
Delay time, CLKR high to internal FSR valid
McBSP2
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
2P
ns
0.45D 0.55D ns
0.45C 0.55C ns
−1
13 ns
−3
24 ns
McBSP1
CLKX int
CLKX ext
−4
13
7
39
M5 t_d(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
McBSP2
CLKX int
CLKX ext
−1
4
2
24 ^ns
M7 t_d(CKXH-DXV)
McBSP3
McBSP1
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted McBSP2
when in Data Delay 0 (XDATDLY=00b) mode.
McBSP3
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
−1
9
2
37
−2
7
7
40
0
10
ns
3
27
−1
10
1
16
M9 t_d(FXH-DXV)
Delay time, FSX high to DX valid^¶
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY=00b) mode.
McBSP1
McBSP2
McBSP3
FSX int
FSX ext
FSX int
FSX ext
FSX int
FSX ext
28
25
30
ns
27
10
27
† _{Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are}
also inverted.
‡ _{P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz.}
§ _{T=CLKRX period = (1 + CLKGDV) * P}
C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶ _{Only DXENA=0 is supported for all OMAP5910 McBSPs.}
August 2002 − Revised August 2004
SPRS197D 143