OMAP5910 Datasheet, PDF (159/166 Pages) Texas Instruments – DUAL-CORE PROCESSOR

Electrical Specifications
5.17 HDQ/1-Wire Interface Timings
Table 5−34 and Table 5−35 assume testing over recommended operating conditions (see Figure 5−36
through Figure 5−39).
Table 5−34. HDQ/1-Wire Timing Requirements^†
H1 t_c
H2 t_v
H3 t_v
Cycle time, master read
Read one data valid after HDQ low
Read zero data hold after HDQ low
H4 t_v Response time from HDQ slave device
OMAP5910 base
frequency = 12 MHz
OMAP5910 base
frequency = 13 MHz
MIN MAX UNIT
190 250 µs
32
50 µs
80 145 µs
190 320 µs
190 303 µs
W1 t_c Cycle time, master read
W2 t_v Read data valid after HDQ low (master sample window)
W3 t_dis Recovery time after slave device inactive
† _{HDQ timing is OMAP5910 default. 1-Wire timing is selectable through software.}
190
µs
12 13.6 µs
1
µs
Table 5−35. HDQ/1-Wire Switching Characteristics
PARAMETER
H5 t_c Cycle time, master write
H6 t_d Write one data valid after HDQ low
H7 t_d Write zero data hold after HDQ low
OMAP5910 base
frequency = 12 MHz
OMAP5910 base
frequency = 13 MHz
H8 t_w Pulse width, HDQ low for break pulse (reset)
H9 t_w Pulse width, HDQ high for break pulse recovery
W4 t_c Cycle time, master write
W5 t_d Write zero master inactive after HDQ low
W6 t_d Write one master inactive after HDQ low
W7 t_dis Recovery time after master inactive
MIN MAX UNIT
190
µs
32
50 µs
100 145 µs
92 145 µs
190
µs
40
µs
190
µs
15
90 µs
1.1 1.4 µs
1
µs
August 2002 − Revised August 2004
SPRS197D 159