OMAP5910 Datasheet, PDF (115/166 Pages) Texas Instruments – DUAL-CORE PROCESSOR

INTERRUPT
RESET
NMI
EMULATOR_TEST
LEVEL2_INTH_FIQ
TC_ABORT
MAILBOX_1 (ARM2DSP1)
Reserved
GPIO
TIMER3
DMA_CHANNEL_1
MPU
Reserved
UART3
WDGTIMER
DMA_CHANNEL_4
DMA_CHANNEL_5
EMIF
LOCAL_BUS
DMA_CHANNEL_0
MAILBOX2 (ARM2DSP2)
DMA_CHANNEL_2
DMA_CHANNEL_3
TIMER2
TIMER1
Functional Overview
Table 3−74. DSP Level 1 Interrupt Mappings
DSP
INTERRUPT
−
−
INT2
INT3
INT4
INT5
INT6
INT7
INT8
INT9
INT10
INT11
INT12
INT13
INT14
INT15
INT16
INT17
INT18
INT19
INT20
INT21
INT22
INT23
DSP
IFR/IMR
REGISTER
BIT
−
−
2
VECTOR
LOCATION
(BYTE
ADDRESS)
FFF00h
FFF08h
FFF10h
PRIORITY
0
1
3
3
FFF18h
5
4
FFF20h
6
5
FFF28h
7
6
FFF30h
9
7
FFF38h
10
8
FFF40h
11
9
FFF48h
13
10
FFF50h
14
11
FFF58h
15
12
FFF60h
17
13
FFF68h
18
14
FFF70h
21
15
FFF78h
22
16
FFF80h
4
17
FFF88h
8
18
FFF90h
12
19
FFF98h
16
20
FFFA0h
19
21
FFFA8h
20
22
FFFB0h
23
23
FFFB8h
24
FUNCTION
DSP Reset Interrupt
DSP Nonmaskable Interrupt
DSP Emulator/Test Interrupt
FIQ Interrupt From DSP Level 2
Handler
Traffic Controller Abort Interrupt
MPU-to-DSP Mailbox 1 Interrupt
Unused, Keep Masked
Interrupt for DSP-Owned Shared
GPIO
DSP Timer 3 Interrupt
DSP DMA Channel 1 Interrupt
MPU Interrupt to DSP
Unused, Keep Masked
UART Interrupt
DSP Watchdog Timer Interrupt
DSP DMA Channel 4 Interrupt
DSP DMA Channel 5 Interrupt
Interrupt for DMA EMIF Interface to
Traffic Controller
Local Bus Interrupt
DSP DMA Channel 0 Interrupt
MPU-to-DSP Mailbox 2 Interrupt
DSP DMA Channel 2 Interrupt
DSP DMA Channel 3 Interrupt
DSP Timer 2 Interrupt
DSP Timer 1 Interrupt
August 2002 − Revised August 2004
SPRS197D 115