OMAP5910 Datasheet, PDF (152/166 Pages) Texas Instruments – DUAL-CORE PROCESSOR

Electrical Specifications
5.12 LCD Controller Timings
Table 5−27 assumes testing over recommended operating conditions (see Figure 5−27 and Figure 5−28).
Table 5−27. LCD Controller Switching Characteristics ^†
NO.
PARAMETER
MIN MAX UNIT
L1
t_{d(CLKH−HSV)}
Delay time, LCD.PCLK high to LCD.HS transition
1
11 ns
L2
t_{d(CLKL−HSV)}
Delay time, LCD.PCLK low to LCD.HS transition
1
11 ns
L3
t_{d(CLKH−VSV)}
Delay time, LCD.PCLK high to LCD.VS transition
1
11 ns
L4
t_{d(CLKL−VSV)}
Delay time, LCD.PCLK low to LCD.VS transition
1
11 ns
L5
t_{d(CLKH−PV)}
Delay time, LCD.PCLK high to pixel data valid (LCD.P[15:0])
11 ns
L6
t_{d(CLKH−PIV)}
Delay time, LCD.PCLK high to pixel data invalid (LCD.P[15:0])
1
ns
L7
t_{d(CLKL−PV)}
Delay time, LCD.PCLK low to pixel data valid (LCD.P[15:0])
11 ns
L8
t_{d(CLKL−PIV)}
Delay time, LCD.PCLK low to pixel data invalid (LCD.P[15:0])
1
ns
L9
t_{d(CLKL−ACV)}
Delay time, LCD.PCLK high to LCD.AC transition
1 5+P^‡ ns
L10 t_{d(CLKL−ACV)}
Delay time, LCD.PCLK low to LCD.AC transition
1 5+P^‡ ns
† _{Although timing diagrams illustrate the logical function of the TFT mode, static timings apply to all supported modes of operation. Likewise,}
LCD.HS, LCD.VS, and LCD.AC are shown as active-low, but each may optionally be configured as active-high.
‡ _{P = period of internal undivided pixel clock}
HSW^†
VSW^†
VFP^†
HFP^†
PPL^†
HBP^†
LCD.PCLK
L4
L4
LCD.VS
L2
L2
LCD.HS
LCD.P[15:0]
L5
L6
D1 D2 D3 Dn
LCD.AC
L9
L9
† _{Delays for HSW (LCD.HS Width), VSW (LCD.VS Width), VFP (Vertical Front Porch), HFP (Horizontal Front Porch), HBP (Horizontal Back Porch)}
and PPL (Pixels per Line) are programmable in number of LCD.PCLK cycles via the LCD configuration registers.
Figure 5−27. TFT Mode (LCD.HS/LCD.VS on Falling and LCD.Px on Rising LCD.PCLK)
152 SPRS197D
August 2002 − Revised August 2004