OMAP5910 Datasheet, PDF (34/166 Pages) Texas Instruments – DUAL-CORE PROCESSOR

Introduction
2.4 Signal Description
Table 2−4 provides a description of the signals on OMAP5910. Many signals are available on multiple pins
depending upon the software configuration of the pin multiplexing options. Ball numbers which are italicized
indicate the default pin muxings at reset. Ball numbers for busses are listed from MSB to LSB (left to right,
top to bottom).
Table 2−4. Signal Description
SIGNAL
GZG GDY
BALL BALL
DESCRIPTION
TYPE^†
EMIFF SDRAM Interface
SDRAM.WE
C3 A1 SDRAM write enable. SDRAM.WE is active (low) during writes, DCAB, and MRS O/Z
commands to SDRAM memory.
SDRAM.RAS
A2 C4 SDRAM row address strobe. SDRAM.RAS is active (low) during ACTV, DCAB,
O/Z
REFR, and MRS commands to SDRAM memory.
SDRAM.DQMU
D4 A2 SDRAM upper data mask. Active-low data mask for the upper byte of the SDRAM O/Z
data bus (SDRAM.D[15:8]). The data mask outputs allow for both 16-bit-wide and
8-bit-wide accesses to SDRAM memories.
SDRAM.DQML
B3 B2 SDRAM lower data mask. Active-low data mask for the lower byte of the SDRAM O/Z
data bus (SDRAM.D[7:0]). The data mask outputs allow for both 16-bit-wide and
8-bit-wide accesses to SDRAM memories.
SDRAM.D[15:0]
D5, D4, SDRAM data bus. SDRAM.D[15:0] provides data exchange between the Traffic
C4, C5, Controller and SDRAM memory.
B4, G8,
D6, B4,
C5, B5,
H8, C6,
C6, A3,
B6, E6,
D7, D6,
C7, A4,
D8, B6,
B8, F7,
G8, C7,
C8, B7,
G9, D7,
B9 A6
I/O/Z
SDRAM.CKE
D9 D7 SDRAM clock enable. Active-high output which enables the SDRAM clock during O/Z
normal operation; SDRAM.CKE is driven inactive to put the memory into
low-power mode.
SDRAM.CLK
C9 A7 SDRAM clock. Clock for synchronization SDRAM memory commands/accesses. I/O/Z
To minimize voltage undershoot and overshoot effects, it is recommended to place
a series resistor (typically ~33 Ω) close to the SDRAM.CLK driver pin.
SDRAM.CLK can also be configured as an input to monitor skew control.
SDRAM.CAS
H9
F8
SDRAM column address strobe. SDRAM.CAS is active (low) during reads, writes, O/Z
and the REFR and MRS commands to SDRAM memory.
SDRAM.BA[1:0]
D10, C9, SDRAM bank address bus. Provides the bank address to SDRAM memories.
O/Z
C10 B8
† _{I = Input, O = Output, Z = High-Impedance}
‡ _{All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain}
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§ _{See Sections 5.6.1 and 5.6.2 for special VSS considerations with oscillator circuits.}
34 SPRS197D
August 2002 − Revised August 2004