OMAP5910 Datasheet, PDF (122/166 Pages) Texas Instruments – DUAL-CORE PROCESSOR

Electrical Specifications
5.2 Recommended Operating Conditions
CV_DD
CV_DD1/2/3/4/A
Device supply voltage, core^†
Low Power Standby mode^‡
Active mode
MIN
1
1.525
NOM
1.1
1.6
MAX
1.675
1.675
UNIT
V
DV_DD1
Device supply voltage, I/O (Peripheral I/O)
2.5
2.75 or 3.3
3.6
V
DV_DD2
DV_DD3
Device supply voltage, I/O (USB transceiver)
Device supply voltage, I/O
(MCSI2, McBSP2, GPIO[9:8])
Low-voltage range^§
High-voltage range^§
3
3.3
3.6
V
1.65
1.8
1.95
V
2.5
2.75 or 3.3
3.6
DV_DD4
Device supply voltage, I/O
(SDRAM interface)
Low-voltage range^§
High-voltage range^§
1.65
1.8
1.95
V
2.5
2.75 or 3.3
3.6
DV_DD5
Device supply voltage, I/O
(FLASH interface)
Low-voltage range^§
High-voltage range^§
1.65
1.8
2
V
2.5
2.75 or 3.3
3.6
CV_DD − DV_DD Device supply voltage difference^¶
DV_DD − CV_DD Device supply voltage difference^¶
1.65
V
2.6
V
V_SS
Supply voltage, GND
0
V
Standard LVCMOS
0.7 DV_DD
DV_DD
Fail-safe LVCMOS
0.7 DV_DD
V_IH
High-level input voltage, I/O
USB.DP, DM (mode 1)
2
I²C
0.7 DV_DD
DV_DD
V
DV_DD
DV_DD
Standard LVCMOS
0
0.3 DV_DD
Fail-safe LVCMOS
0
V_IL
Low-level input voltage, I/O
USB.DP, DM (mode 1)
0
0.3 DV_DD
V
0.8
I²C
0
0.3 DV_DD
V_I
Input voltage
USB.DP, DM (mode 2)
0.8
OSC1 and OSC32K pins
2.5
V
CV_DD
V_ID
Differential input voltage, I/O
USB.DP, DM (mode 2)
200
mV
2-mA drive strength buffers
−2
4-mA drive strength buffers
I_OH
High-level output current
8-mA drive strength buffers
18.3-mA drive strength
buffers
−4
−8
mA
−18.3
2-mA drive strength buffers
2
4-mA drive strength buffers
4
6-mA drive strength buffers
I_OL
Low-level output current
8-mA drive strength buffers
6
mA
8
18.3-mA drive strength
buffers
18.3
T_C
Operating case temperature
−40
85
°C
† _{All core voltage supplies should be tied to the same voltage level (within 0.3 V).}
‡ _{Low Power Standby is defined as follows: the device is in Deep Sleep mode and LOW_PWR = 1. The device runs from 32 kHz clock in this mode.}
§ _{High and low voltage ranges are selectable via software configuration.}
¶ _{In systems where the CVDDx and DVDDx power supplies are ramped at generally the same time (within 500 ms of one another), there are no}
specific power sequencing requirements for the supplies. The only sequencing requirement is that the maximum voltage difference between
CV_DD and DV_DD is not exceeded for greater than 500 ms. Likewise, if different voltages are used for the separate DV_DDx supplies, all DV_DDx
supplies should be ramp up to valid voltage levels within 500 ms of one another.
122 SPRS197D
August 2002 − Revised August 2004