OMAP5910 Datasheet, PDF (36/166 Pages) Texas Instruments – DUAL-CORE PROCESSOR

Introduction
Table 2−4. Signal Description (Continued)
SIGNAL
GZG GDY
BALL BALL
DESCRIPTION
TYPE^†
EMIFS FLASH and Asynchronous Memory Interface (Continued)
FLASH.A[24:1]
L7, J3, EMIFS address bus. Address output bus for all EMIFS accesses. FLASH.A[24:1] O/Z
K3, J4, provides the upper 24 bits of a 25-bit byte address. The byte enables must be
K4, H6, used to implement 8-bit accesses.
L8, H5,
J1, H2,
J3, H4,
J4, H3,
J2, G2,
K7, G1,
H3, G5,
H4, G3,
K8, G4,
G2, E1,
G3, F2,
G4, F4,
F3, F3,
J7, F5,
E3, D2,
F4, E4,
D2, E3,
E4, C2,
C1, C1,
D3, G6,
J8
B1
FLASH.RDY
H7 C3 EMIFS ready. Active-high ready input used to suspend the EMIFS interface when
I
the external memory or asynchronous device is not ready to continue the current
cycle. It is recommended that this pin should be pulled high externally and
unused. See the OMAP5910 Dual-Core Processor Silicon Errata (literature
number SPRZ016) for more details.
LCD Interface
LCD.VS
D14 D11 LCD vertical sync output. LCD.VS is the frame clock which signals the start of a
O
new frame of pixels to the LCD panel. In TFT mode, LCD.VS is the vertical
synchronization signal.
LCD.HS
H12 E11 LCD horizontal sync. LCD.HS is the line clock which signals the end of a line of
O
pixels to the LCD panel. In TFT mode, LCD.HS is the horizontal synchronization
signal.
LCD.AC
B15 A11 LCD AC-bias. LCD.AC is used to signal the LCD to switch the polarity of the row
O
and column power supplies to counteract charge buildup causing DC offset. In
TFT mode, LCD.AC is used as the output enable to latch LCD pixel data using the
pixel clock.
LCD.PCLK
C15 A12 LCD pixel clock output. Clock output provided to synchronize pixel data to the
O
LCD panel. In passive mode, LCD.PCLK only transitions when LCD.P[15:0] is
valid. In active mode, LCD.PCLK transitions continuously and LCD.AC is used as
the output enable when LCD.P[15:0] is valid.
† _{I = Input, O = Output, Z = High-Impedance}
‡ _{All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain}
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§ _{See Sections 5.6.1 and 5.6.2 for special VSS considerations with oscillator circuits.}
36 SPRS197D
August 2002 − Revised August 2004