OMAP5910 Datasheet, PDF (134/166 Pages) Texas Instruments – DUAL-CORE PROCESSOR

Electrical Specifications
FLASH.CLK^†
(internal)
F1
FLASH.CSx
F2
FLASH.BE[1:0]
F4
FLASH.A[24:3]
F4
FLASH.A[2:1]
FLASH.D[15:0]
FLASH.ADV
FLASH.OE
M cycles^‡
P cycles^‡
P cycles^‡
P cycles^‡
F1
F5
Word 0
F6
D1
F8
Valid
A1
F4
Word 1
F7
D2
F3
F5
F5
Word 2 Word 3
F6
F7
D3
D4
F8
F9
F9
FLASH.WE
† _{FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to}
express relative timings.
‡ _{Number of cycles is configurable via EMIFS setup registers.}
Figure 5−9. Asynchronous Read − Page Mode ROM
134 SPRS197D
August 2002 − Revised August 2004