OMAP5910 Datasheet, PDF (160/166 Pages) Texas Instruments – DUAL-CORE PROCESSOR

Electrical Specifications
HDQ
Read 1
Read 0
H2
H3
H1
Figure 5−36. OMAP5910 HDQ Interface Reading From HDQ Slave Device
HDQ
Write 1
Write 0
H6
H7
H5
Figure 5−37. OMAP5910 HDQ Interface Writing to HDQ Slave Device
HDQ
Break
0
(LSB)
Command Byte
(Written by OMAP5910)
Register Address
1
6
7
(MSB)
Data Byte
(Received by OMAP5910 from Slave)
0
1
(LSB)
6
7
(MSB)
H4
Figure 5−38. Typical Communication Between OMAP5910 HDQ and HDQ Slave
HDQ
HH192
HH181
Figure 5−39. HDQ/1-Wire Break (Reset) Timing
160 SPRS197D
August 2002 − Revised August 2004