TL16CP754C Datasheet, PDF (7/49 Pages) Texas Instruments – QUAD UARTS WITH 64-BYTE FIFO

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TL16CP754C, TL16CM754C, TL16C754C
SLLS644E – DECEMBER 2007 – REVISED MAY 2010
A. The vote logic determines whether the RX data is a logic 1 or 0. It takes three samples of the RX line and uses a
majority vote to determine the logic level received. The Vote logic operates on all bits received.
FUNCTIONAL DESCRIPTION
The '754C UART is pin compatible with the TL16C754B and ST16C654 UARTs. It provides more enhanced
features. All additional features are provided through a special enhanced feature register.
The UART performs serial-to-parallel conversion on data characters received from peripheral devices or modems
and parallel-to-parallel conversion on data characters transmitted by the processor. The complete status of each
channel of the '754C UART can be read at any time during functional operation by the processor.
The '754C UART can be placed in an alternate mode (FIFO mode) relieving the processor of excessive software
overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can store up to
64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or
programmable trigger levels. Primary outputs RXRDY and TXRDY allow Signaling of DMA transfers.
The '754C UART has selectable hardware flow control and software flow control. Both schemes significantly
reduce software overhead and increase system efficiency by automatically controlling serial data flow. Hardware
flow control uses the RTS output and CTS input signals. Software flow control uses programmable Xon/Xoff
characters.
The UART includes a programmable baud rate generator that can divide the timing reference clock input by a
divisor between 1 and (2¹⁶–1). The CLKSEL pin can be used to divide the input clock by 4 or by 1 to generate
the reference clock during the reset. The divide-by-4 clock is selected when CLKSEL pin is a logic 0 or the
divide-by-1 is selected when CLKSEL is a logic 1.
Trigger Levels
The '754C UART provides independent selectable and programmable trigger levels for both receiver and
transmitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in
effect, the trigger level is the default value of one byte. The selectable trigger levels are available via the FCR.
The programmable trigger levels are available via the TLR.
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Product Folder Link(s): TL16CP754C TL16CM754C TL16C754C