TL16CP754C Datasheet, PDF(12/49 Page) Texas Instruments

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TL16CP754C Datasheet, PDF (12/49 Pages) Texas Instruments – QUAD UARTS WITH 64-BYTE FIFO

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TL16CP754C, TL16CM754C, TL16C754C

SLLS644E â DECEMBER 2007 â REVISED MAY 2010

Table 2. Register Reset Functions(1)

Interrupt enable register

Interrupt identification register

FIFO control register

Line control register

Modem control register

Line status register

Modem status register

Enhanced feature register

Receiver holding register

Transmitter holding register

Transmission control register

Trigger level register

Alternate function register

RESET

CONTROL

RESET

RESET STATE

All bits cleared

Bit 0 is set. All other bits cleared.

All bits cleared

Reset to 00011101 (1D hex).

Bit 6â0 cleared. Bit 7 reflects the inverse of the

CLKSEL pin value.

Bits 5 and 6 set. All other bits cleared.

Bits 0â3 cleared. Bits 4â7 input signals.

Bit 6â0 is cleared. Bit 7 reflects the inverse of the

CLKSEL pin value.

Pointer logic cleared

All bits cleared

All bits (except AFR4) cleared; AFR4 set

(1) Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, Xoff2 are not reset by the top-level reset signal RESET,

i.e., they hold their initialization values during reset.

Table 3 summarizes the state of outputs after reset.

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SIGNAL

RTS

DTR

RXRDY

TXRDY

Table 3. Signal Reset Functions

RESET CONTROL

RESET

RESET STATE

High

Low

Interrupts

The '754C UART has interrupt generation and prioritization (six prioritized levels of interrupts) capability. The

interrupt enable register (IER) enables each of the six types of interrupts and the INT signal in response to an

interrupt generation. The IER also can disable the interrupt system by clearing bits 0â3, 5â7. When an interrupt

is generated, the interrupt identification register(IIR) indicates that an interrupt is pending and provides the type

of interrupt through IIR[5â0]. Table 4 summarizes the interrupt control functions.

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