TL16CP754C Datasheet, PDF (3/49 Pages) Texas Instruments – QUAD UARTS WITH 64-BYTE FIFO

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TL16CP754C, TL16CM754C, TL16C754C
SLLS644E – DECEMBER 2007 – REVISED MAY 2010
NAME
A0
TERMINAL
NO.
PN
PM
30
24
A1
29
23
A2
28
22
CDA, CDB,
CDC, CDD
79, 23,
39, 63
64, 19,
31, 49
CLKSEL
26
21
CSA, CSB,
CSC, CSD
9, 13,
49, 53
7, 11,
38, 42
CTSA, CTSB,
CTSC, CTSD
4, 18,
44, 58
2, 16,
33, 47
D0–D2,
D3–D7
68–70,
71–75
53–60
TERMINAL FUNCTIONS
I/O DESCRIPTION
I
Address bit 0 select. Internal registers address selection. Refer to Table 9 for Register
Address Map.
I
Address bit 1 select. Internal registers address selection. Refer to Table 9 for Register
Address Map.
I
Address bit 2 select. Internal registers address selection. Refer to Table 9 for Register
Address Map.
Carrier detect (active low). These inputs are associated with individual UART channels A
I through D. A low on these pins indicates that a carrier has been detected by the modem
for that channel.
Clock select. CLKSEL selects the divide-by-1 or divide-by-4 prescalable clock. During
the reset, a logic 1 (V_CC) on CLKSEL selects the divide-by-1 prescaler. A logic 0 (GND)
I
on CLKSEL selects the divide-by-4 prescaler. The value of CLKSEL is latched into
MCR[7] at the trailing edge of RESET. A logic 1 (V_CC) on CLKSEL will latch a 0 into
MCR[7]. A logic 0 (GND) on CLKSEL will latch a 1 into MCR[7]. MCR[7] can be changed
after RESET to alter the prescaler value.
Chip select A, B, C, and D (active low). These pins enable data transfers between the
I user CPU and the '754C for the channel(s) addressed. Individual UART sections (A, B,
C, D) are addressed by providing a low on the respective CSA through CSD pin.
Clear to send (active low). These inputs are associated with individual UART channels A
through D. A low on the CTS pins indicates the modem or data set is ready to accept
I transmit data from the '754C. Status can be checked by reading MSR[4]. These pins
only affect the transmit and receive operations when auto CTS function is enabled
through the enhanced feature register (EFR[7]), for hardware flow control operation.
Data bus (bidirectional). These pins are the eight-bit, 3-state data bus for transferring
I/O information to or from the controlling CPU. D0 is the least significant bit and the first data
bit in a transmit or receive serial data stream.
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