TL16CP754C Datasheet, PDF (34/49 Pages) Texas Instruments – QUAD UARTS WITH 64-BYTE FIFO

TL16CP754C, TL16CM754C, TL16C754C
SLLS644E – DECEMBER 2007 – REVISED MAY 2010
www.ti.com
LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors
remaining in the FIFO.
NOTE
Reading the LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO
read pointer is incremented by reading the RHR.
Modem Control Register (MCR)
The MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem.
Table 14 shows modem control register bit settings.
Table 14. Modem Control Register (MCR) Bit Settings⁽¹⁾
BIT NO.
0
1
2
3
4
5
6
7
BIT SETTINGS
0 = Force DTR output to inactive (high)
1 = Force DTR output to active (low). In loopback controls MSR[5].
0 = Force RTS output to inactive (high)
1 = Force RTS output to active (low).
In loopback controls MSR[4].
If Auto-RTS is enabled the RTS output is controlled by hardware flow control
0 Disables the FIFORdy register
1 Enable the FIFORdy register.
In loopback controls MSR[6].
0 = Forces the IRQ(A–D) outputs to high-impedance state
1 = Forces the IRQ(A–D) outputs to the active state.
In loopback controls MSR[7].
0 = Normal operating mode
1 = Enable local loopback mode (internal)
In this mode the MCR[3:0] signals are looped back into MSR[3:0] and the TX output is looped back to the RX input
internally.
0 = Disable Xon Any function
1 = Enable Xon Any function
0 = No action
1 = Enable access to the TCR and TLR registers.
0 = Divide by one clock input
1 = Divide by four clock input
This bit reflects the inverse of the CLKSEL pin value at the trailing edge of the RESET pulse.
(1) MCR[7:5] can only be modified when EFR[4] is set i.e., EFR[4] is a write enable.
34
Submit Documentation Feedback
Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): TL16CP754C TL16CM754C TL16C754C