TL16CP754C Datasheet, PDF (14/49 Pages) Texas Instruments – QUAD UARTS WITH 64-BYTE FIFO

TL16CP754C, TL16CM754C, TL16C754C
SLLS644E – DECEMBER 2007 – REVISED MAY 2010
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Figure 6. FIFO Polled Mode Operation
DMA Signaling
There are two modes of DMA operation, DMA mode 0 or 1, selected by FCR[3].
In DMA mode 0 or FIFO disable (FCR[0]=0) DMA occurs in single character transfers. In DMA mode 1
multicharacter (or block) DMA transfers are managed to relieve the processor for longer periods of time.
Single DMA Transfers (DMA Mode0/FIFO Disable)
Transmitter: When empty, the TXRDY signal becomes active. TXRDY goes inactive after one character has
been loaded into it.
Receiver: RXRDY is active when there is at least one character in the FIFO. It becomes inactive when the
receiver is empty.
Figure 7 shows TXRDY and RXRDY in DMA mode 0/FIFO disable.
Figure 7. TXRDY and RXRDY in DMA Mode 0/FIFO Disable
Block DMA Transfers (DMA Mode1)
Transmitter: TXRDY is active when a trigger level number of spaces are available. It becomes inactive when the
FIFO is full.
Receiver: RXRDY becomes active when the trigger level has been reached or when a timeout interrupt occurs. It
goes inactive when the FIFO is empty or an error in the RX FIFO is flagged by LSR(7).
Figure 8 shows TXRDY and RXRDY in DMA mode 1.
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