TL16CP754C Datasheet, PDF (4/49 Pages) Texas Instruments – QUAD UARTS WITH 64-BYTE FIFO

TL16CP754C, TL16CM754C, TL16C754C
SLLS644E – DECEMBER 2007 – REVISED MAY 2010
www.ti.com
NAME
TERMINAL
NO.
PN
PM
DSRA, DSRB,
DSRC, DSRD
3, 19,
43, 59
1, 17,
32, 48
DTRA, DTRB,
DTRC, DTRD
5, 17,
45, 57
3, 15,
34, 46
GND
INTA, INTB,
INTC, INTD
16, 36,
56, 76
14, 28,
45, 61
8, 14,
48, 54
6, 12,
37, 43
INTSEL
67
–
IOR
IOW
RESET
RIA, RIB,
RIC, RID
51
40
11
9
33
27
78, 24,
38, 64
63, 19,
30, 50
RTSA, RTSB,
RTSC, RTSD
7, 15,
47, 55
5, 13,
36, 44
RXA, RXB,
RXC, RXD
77, 25,
37, 65
62, 20,
29, 51
RXRDY
34
–
TXA, TXB,
TXC, TXD
10, 12,
50, 52
8, 10,
39, 41
TXRDY
35
–
TERMINAL FUNCTIONS (continued)
I/O DESCRIPTION
Data set ready (active low). These inputs are associated with individual UART channels
I A through D. A low on these pins indicates the modem or data set is powered on and is
ready for data exchange with the UART.
Data terminal ready (active low). These outputs are associated with individual UART
channels A through D. A low on these pins indicates that the '754C is powered on and
O
ready. These pins can be controlled through the modem control register. Writing a 1 to
MCR[0] sets the DTR output to low, enabling the modem. The output of these pins is
high after writing a 0 to MCR[0], or after a reset. These pins can also be used in the
RS-485 mode to control an external RS-485 driver or transceiver.
Pwr Power signal and power ground
Interrupt A, B, C, and D (active high). These pins provide individual channel interrupts,
INTA-D. INTA−D are enabled when MCR[3] is set to a 1, interrupts are enabled in the
O interrupt enable register (IER) and when an interrupt condition exists. Interrupt conditions
include: receiver errors, available receiver buffer data, transmit buffer empty, or when a
modem status flag is detected. INTA−D are in the high-impedance state after reset.
Interrupt select (active high with internal pulldown). INTSEL can be used in conjunction
with MCR[3] to enable or disable the 3-state interrupts INTA-D or override MCR[3] and
I force continuous interrupts. Interrupt outputs are enabled continuously by making this pin
a 1. Driving this pin low allows MCR[3] to control the 3-state interrupt output. In this
mode, MCR[3] is set to a 1 to enable the 3-state outputs.
Read input (active low strobe). A valid low level on IOR loads the contents of an internal
I register defined by address bits A0–A2 onto the '754C data bus (D0–D7) for access by
an external CPU.
Write input (active low strobe). A valid low level on IOW transfers the contents of the
I data bus (D0–D7) from the external CPU to an internal register that is defined by
address bits A0–A2.
Reset. RESET resets the internal registers and all the outputs. The UART transmitter
I output and the receiver input are disabled during reset time. See '754C external reset
conditions for initialization details. RESET is an active high input.
Ring indicator (active low). These inputs are associated with individual UART channels A
I
through D. A low on these pins indicates the modem has received a ringing signal from
the telephone line. A low-to-high transition on these input pins generates a modem
status interrupt, if it is enabled.
Request to send (active low). These outputs are associated with individual UART
channels A through D. A low on the RTS pins indicates the transmitter has data ready
O
and waiting to send. Writing a 1 in the modem control register (MCR[1]) sets these pins
to low, indicating data is available. After a reset, these pins are set to 1. These pins only
affect the transmit and receive operation when auto-RTS function is enabled through the
enhanced feature register (EFR[6]), for hardware flow control operation.
Receive data input. These inputs are associated with individual serial channel data to
the '754C. During the local loopback mode, these RX input pins are disabled and TX
I data is internally connected to the UART RX input internally. During normal mode, RXn
should be held high when no data is being received. These outputs also can be used in
IrDA mode. See the IrDA mode section for more information.
Receive ready (active low). RXRDY contains the wire-ORed status of all four receive
O
channel FIFOs, RXRDY A–D. It goes low when the trigger level has been reached or a
timeout interrupt occurs. It goes high when all RX FIFOs are empty and there is an error
in RX FIFO.
Transmit data. These outputs are associated with individual serial transmit channel data
from the '754C. During the local loopback mode, the TX input pin is disabled and TX
O
data is internally connected to the UART RX input. During normal mode, TXn is high
when no data is being sent. These outputs can also be used in IrDA mode, in which
case TXn is low when no data is being sent. See the IrDA mode section for more
information.
Transmit ready (active low). TXRDY contains the wire-ORed status of all four transmit
O channel FIFOs, TXRDY A–D. It goes low when there are a trigger level number of
spares available. It goes high when all four TX buffers are full.
4
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