TL16CP754C Datasheet, PDF (15/49 Pages) Texas Instruments – QUAD UARTS WITH 64-BYTE FIFO

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TL16CP754C, TL16CM754C, TL16C754C
SLLS644E – DECEMBER 2007 – REVISED MAY 2010
Figure 8. TXRDY and RXRDY in DMA Mode 1
Sleep Mode
Sleep mode is an enhanced feature of the '754C UART. It is enabled when EFR[4], the enhanced functions bit, is
set and when IER[4] is set. Sleep mode is entered when:
• The serial data input line, RX, is idle (see break and time-out conditions).
• The TX FIFO and TX shift register are empty.
• There are no interrupts pending except THR and timeout interrupts.
Sleep mode is not entered if there is data in the RX FIFO.
In sleep mode the UART clock and baud rate clock are stopped. Because most registers are clocked using these
clocks the power consumption is greatly reduced. The UART wakes up when any change is detected on the RX
line, when there is any change in the state of the modem input pins or if data is written to the TX FIFO.
NOTE
Writing to the divisor latches, DLL and DLH, to set the baud clock, must not be done
during sleep mode. Therefore it is advisable to disable sleep mode using IER[4] before
writing to DLL or DLH.
Break and Timeout Conditions
An RX timeout condition is detected when the receiver line, RX, has been high for a time equivalent to (4 ×
programmed word length) + 12 bits and there is at least one byte stored in the Rx FIFO.
When a break condition occurs, the TX line is pulled low. A break condition is activated by setting LCR[6].
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