TL16CP754C Datasheet, PDF (30/49 Pages) Texas Instruments – QUAD UARTS WITH 64-BYTE FIFO

TL16CP754C, TL16CM754C, TL16C754C
SLLS644E – DECEMBER 2007 – REVISED MAY 2010
PRINCIPLES OF OPERATION
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Register Map
Each register is selected using address lines A[0], A[1], A[2] and, in some cases, bits from other registers. The
programming combinations for register selection are shown in Table 9.
Table 9. Register Map – Read/Write Properties⁽¹⁾
A[2]
A[1]
A[0]
READ MODE
WRITE MODE
0
0
0
Receive holding register (RHR)
Transmit holding register (THR)
0
0
1
Interrupt enable register (IER)
Interrupt enable register
0
1
0
Interrupt identification register (IIR)
FIFO control register (FCR)
0
1
1
Line control register (LCR)
Line control register
1
0
0
Modem control register (MCR)
Modem control register
1
0
1
Line status register (LSR)
1
1
0
Modem status register (MSR)
1
1
1
Scratch register (SPR)
Scratch register (SPR)
0
0
0
Divisor latch LSB (DLL)
Divisor latch LSB (DLL)
0
0
1
Divisor latch MSB (DLH)
Divisor latch MSB (DLH)
0
1
0
Alternate function register (AFR)
Alternate function register (AFR)
0
1
0
Enhanced feature register (EFR)
Enhanced feature register
1
0
0
Xon-1 word
Xon-1 word
1
0
1
Xon-2 word
Xon-2 word
1
1
0
Xoff-1 word
Xoff-1 word
1
1
1
Xoff-2 word
Xoff-2 word
1
1
0
Transmission control register (TCR)
Transmission control register
1
1
1
Trigger level register (TLR)
Trigger level register
1
1
1
FIFO ready register
(1) DLL and DLH are accessible only when LCR bit 7 is 1, and AFR is only accessible when LCR[7:5] = 100.
Enhanced feature register, Xon1, 2 and Xoff1, 2 are accessible only when LCR is set to 10111111 (8hBF).
Transmission control register and trigger level register are accessible only when EFR[4] = 1 and MCR[6] = 1, i.e. EFR[4] and MCR[6]
are read/write enables.
FCR FIFORdy register is accessible when any CS A–D = 0, MCR[2] = 1 and loopback MCR [4] = 0 is disabled.
MCR[7] can only be modified when EFR[4] is set.
Table 10 lists and describes the '754C internal registers.
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