TL16CP754C Datasheet, PDF (38/49 Pages) Texas Instruments – QUAD UARTS WITH 64-BYTE FIFO

TL16CP754C, TL16CM754C, TL16C754C
SLLS644E – DECEMBER 2007 – REVISED MAY 2010
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Alternate Function Register (AFR)
The alternate function register (AFR) is used to enable some extra functionality beyond the capabilities of the
original TL16C754. The first of these is a concurrent write mode, which can be useful in more expediently setting
up all four UART channels. The second addition is the IrDA mode, which supports Standard IrDA (SIR) mode
with baud rates from 2400 to 115.2 bps. The third addition is support for RS-485 bus drivers or transceivers by
providing an output pin (DTRx) per channel, which is timed to keep the RS-485 driver enabled as long as
transmit data is pending.
The AFR is located at A[2:0] = 010 when LCR[7:5] = 100.
BIT NO.
0
1
2
3
4
7:5
Table 23. Alternate Function Register (AFR) Bit Settings
BIT SETTINGS
CONC enables the concurrent write of all four (754) or two (752) channels simultaneously,
which helps speed up initialization. Ensure that any indirect addressing modes have been
enabled before using.
IREN enables the IrDA SIR mode. This mode is only specified to 115.2 bps and use of this
mode at higher speeds is not recommended.
485EN enables the half duplex RS-485 mode and causes the DTRx output to be set high
whenever there is any data in the THR or TSR and to be held high until the delay set by
DLY3:0 has expired, at which time it will be set low. The DTRx output is intended to drive
the enabled input of an RS-485 driver. When this bit is set, the transmitter interrupts will be
held off until the TSR is empty, unless 485LG is set.
485LG is set when the 485EN is set. This bit indicates that a relatively large data block is
being set, requiring more than a single load of the xmt fifo. In this case, the transmitter
interrupts occur as in the standard RS-232 mode, either when the xmt fifo contents drop
below the xmt threshold or when the xmt fifo is empty.
RCVEN is valid only when 485EN or IREN is set, and allows the serial receiver to listen in
or snoop on the RS485 traffic or IrDA traffic. RS485 mode is generally considered half
duplex, and usually a node is either driving or receiving, but there can be cases when it is
advantageous to verify what you are sending. This can be used to detect collisions or as
part of an arbitration mechanism on the bus. When both RCVEN and 485EN are set, the
receiver will store any data presented on RX, if any. Note that implies that the external
RS485 receiver is enabled. Whenever 485EN is cleared, the serial receiver is enabled for
normal full duplex RS232 traffic. If RCVEN is cleared while 485EN is set, the receiver will
be disabled while that channel is transmitting. Standard IrDA (SIR) is also considered half
duplex. Often the light energy from the transmitting LED is coupled back into the receiving
PIN diode, which creates an input data stream that is not of interest to the host. Disabling
the receiver (clearing RCVEN) prevents this reception, and eliminates the task of unloading
the data. On the other hand, for diagnostic or other purposes, it may be useful to observe
this data stream. For example, a mirror could be used to intentionally couple the output LED
to the input PIN. For these cases, RCVEN could be set to enable the receiver.
NOTE: When RCVEN is cleared (set to 0), the character timeout interrupt is not available,
even in RSA-232 mode. This can be useful when checking code for valid threshold
interrupts, as the timeout interrupt will not override the threshold interrupt.
DLY3–DLY0 sets a delay after the last stop bit of the last data byte being set before the
DTRx is set low, to allow for long cable runs. The delay is in number of bit times and is
enabled by 485EN. The delay will start only when both the xmt serial shift register (TSR) is
empty and the xmt fifo (THR) is empty, and if started, will be cleared by any data being
written to the THR.
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