TL16CP754C Datasheet, PDF (41/49 Pages) Texas Instruments – QUAD UARTS WITH 64-BYTE FIFO

TL16CP754C, TL16CM754C, TL16C754C
www.ti.com
SLLS644E – DECEMBER 2007 – REVISED MAY 2010
start, data, or stop bits. The IrDA engine in the ’754C evaluate only single bits and only follow the 115.2 kbps
protocol. The 115.2 kbps rate is a maximum rate. When both ends of the transfer are set up to a lower but
matching speed, the protocol still works. The clock used to code or sample the data is 16 times the baud rate, or
1.843 MHz maximum. To code a 1, no pulse is sent or received for 1-bit time period, or 16 clock cycles. To code
a 0, one pulse is sent or received within a 1-bit time period, or 16 clock cycles. The pulse must be at least 1.6 ms
wide and 3 clock cycles long at 1.843 MHz. At lower baud rates the pulse can be 1.6 ms wide or as long as 3
clock cycles. The transmitter output, Tx, is intended to drive a LED circuit to generate an infrared pulse. The LED
circuits work on positive pulses. A terminal circuit is expected to create the receiver input, Rx. Most, but not all,
PIN circuits have inversion and generate negative pulses from the detected infrared light. Their output is normally
high. The '754C can decode either negative or positive pulses on Rx.
IrDA Encoder Function
Serial data from a UART is encoded to transmit data to the optoelectronics. While the serial data input to this
block (Int_Tx) is high, the output (Tx) is always low, and the counter used to form a pulse on Tx is continuously
cleared. After Int_Tx resets to 0, Tx rises on the falling edge of the seventh 16XCLK. On the falling edge of the
tenth 16XCLK pulse, Tx falls, creating a 3-clock-wide pulse. While Int_Tx stays low, a pulse is transmitted during
the seventh to tenth clocks of each 16-clock bit cycle.
Figure 28. IrDA-SIR Encoding Scheme – Detailed
Timing Diagram
Figure 29. Encoding Scheme – Macro View
After reset, Int_Rx is high and the 4-bit counter is cleared. When a falling edge is detected on Rx, Int_Rx falls on
the next rising edge of 16XCLK with sufficient setup time. Int_Rx stays low for 16 cycles (16XCLK) and then
returns to high as required by the IrDA specification. As long as no pulses (falling edges) are detected on Rx,
Int_Rx remains high.
Figure 30. IrDA-SIR Decoding Scheme – Detailed
Timing Diagram
Figure 31. IrDA-SIR Decoding Scheme – Macro
View
It is possible for jitter or slight frequency differences to cause the next falling edge on Rx to be missed for one
16XCLK cycle. In that case, a 1-clock-wide pulse appears on Int_Rx between consecutive zeroes. It is important
for the UART to strobe Int_Rx in the middle of the bit time to avoid latching this 1-clock-wide pulse. The
TL16C550C UART already strobes incoming serial data at the proper time. Otherwise, note that data is required
to be framed by a leading zero and a trailing one. The falling edge of that first zero on Int_Rx synchronizes the
read strobe. The strobe occurs on the eighth 16XCLK pulse after the Int_Rx falling edge and once every 16
cycles thereafter until the stop bit occurs.
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